Hi OpenRISC gurus:
I'd like to have a configurable watchdog in my OR10 SoC. Can anyone
recommend me an existing implementation?
Connecting the watchdog over the Wishbone bus could consume more FPGA
resources than the watchdog implementation itself, I wonder if this is
something we could add to the OpenRISC arquitecture. Could anyone
recommend me a good watchdog API? Apart from a "l.watchdog_reset"
instruction, I guess some SPR would be needed to configure the watchdog
period. Some processors also have a "reset reason" register where one
can find out whether the last reset was triggered by the watchdog.
Thanks in advance,
rdiez
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