On Sat, Oct 6, 2012 at 11:24 PM, Stefan Kristiansson < [email protected]> wrote:
> > One feature of interest that you haven't mentioned is > the ability to choose if a watchdog timeout should > cause a reset or an interrupt. > > Stefan > _______________________________________________ > You want both. First try a interrupt and if that works then you are fine. If not then you do the reset. You might need a watchdog on the watchdog in case the interrupt routine can tickle the WD to disable the reset but is unable to fully restore the system. That can put you into an infinite loop. You want your watchdog solution to contain several layers of hardware and software that gets progressively more aggressive until the system responds. Where it gets tricky is if your fpga is only one of several chips that gets its power up reset from a source on the Printed Circuit board. This means that your chip must be able to drive out a reset onto its own reset input when the watchdog bites. ( bark=interrupt, bite=reset). So in this case the watchdog reset has to be designed to work from any starting state since it will not have any powerup reset signal. That means that you will need to create a special simulation-test reset in order to reset the watchdog at powerup John Eaton
_______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
