On Sat, Oct 06, 2012 at 07:09:54PM +0200, R. Diez wrote: > Hi OpenRISC gurus: > > I'd like to have a configurable watchdog in my OR10 SoC. Can anyone > recommend me an existing implementation? > > Connecting the watchdog over the Wishbone bus could consume more > FPGA resources than the watchdog implementation itself, I wonder if > this is something we could add to the OpenRISC arquitecture. Could > anyone recommend me a good watchdog API? Apart from a > "l.watchdog_reset" instruction, I guess some SPR would be needed to > configure the watchdog period. Some processors also have a "reset > reason" register where one can find out whether the last reset was > triggered by the watchdog. >
I think the whole watchdog functionality could (and should) be handled through sprs (if not through wb, I'm not 100% convinced about the resource savings here, but I haven't looked at it so you might be right) and not by adding new instructions. One feature of interest that you haven't mentioned is the ability to choose if a watchdog timeout should cause a reset or an interrupt. Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
