Components should NEVER halt a simulation for any reason. It really causes problems when you go to multicore where processors are jumping in and out of halt state all the time. You also do not want to halt on the first error because you may still want to get data from other parts of the design.
A component should set a halt flag and let the simulation itself decide if it should halt. Then it reports the clock cycle, instance and reason for the halt before giving you a tally of how many errors occurred during the run. The uart is a bad idea because of the variable delay until its ready to send and the rather large character delay. If I am doing performance benchmarking or checking that a change had zero effect on the runtime then I need to know the exact cycle that it reaches the halt instruction. John Eaton On Fri, Nov 30, 2012 at 5:56 PM, Peter Gavin <[email protected]> wrote: > Hi guys, > > Since we're doing ISA updates, I think might be useful to add a halt > instruction. In the simulator, it could be used to actually halt the > simulation. In a real CPU, this should probably just put the CPU to sleep > until an interrupt occurs. > > I also think we should deprecate the l.nop hacks we have everywhere in the > various simulators. They're primarily used for I/O and halting the > simulator. Since pretty much every implementation includes a UART, and a > UART is pretty easy to implement, perhaps we should (for example) modify > the or1ksim testsuite to output its diagnostic messages on the UART instead > of using nops. This would also help with building a testsuite that can run > on both simulators and real systems. > > What do you guys think? > > -Pete > > _______________________________________________ > OpenRISC mailing list > [email protected] > http://lists.openrisc.net/listinfo/openrisc > >
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