On Sat, Dec 1, 2012 at 10:46 AM, Ouabache Designworks <[email protected]>wrote:
> > Components should NEVER halt a simulation for any reason. It really causes > problems when you go to multicore where processors are jumping in and out > of halt state all the time. You also do not want to halt on the first error > because you may still want to get data from other parts of the design. > > A component should set a halt flag and let the simulation itself decide if > it should halt. Then it reports the clock cycle, instance and reason for > the halt before giving you a tally of how many errors occurred during the > run. > Sure. That's why I mentioned a real CPU should just go to sleep until an interrupt occurs. A multicore simulator would monitor the state of all cores and could put off halting until it's ok to do so. But for or1ksim, the NOP_EXIT code just causes exit to be called. :) > > The uart is a bad idea because of the variable delay until its ready to > send and the rather large character delay. Yeah, but there are times where it's useless (real systems and netlist simulations). It can be made an option in the testsuite that would allow either case. > If I am doing performance benchmarking or checking that a change had zero > effect on the runtime then I need to know the exact cycle that it reaches > the halt instruction. > > An actual l.halt instruction would still allow that, the same way as the l.nop NOP_EXIT does. -Pete
_______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
