> -----Original Message-----
> From: Steve Gordon [mailto:sgor...@redhat.com]
> Sent: Wednesday, February 11, 2015 8:49 PM
> To: OpenStack Development Mailing List (not for usage questions)
> Cc: Znoinski, Waldemar
> Subject: Re: [openstack-dev] Testing NUMA, CPU pinning and large pages
> 
> ----- Original Message -----
> > From: "Adrian Hoban" <adrian.ho...@intel.com>
> >
> > Hi Folks,
> >
> > I just wanted to share some details on the Intel CI testing strategy for 
> > NFV.
> >
> > You will see two Intel CIs commenting:
> > #1: Intel-PCI-CI
> > - Yongli He and Shane Wang are leading this effort for us.
> > - The focus in this environment is on PCIe and SR-IOV specific testing.
> > - Commenting back to review.openstack.org has started.
> 
> With regards to SR-IOV / PCI specifically it seemed based on
> https://review.openstack.org/#/c/139000/ and
> https://review.openstack.org/#/c/141270/ that there was still some
> confusion as to where the tests should actually live (and I expect the same is
> true for the NUMA, Large Pages, etc. tests). Is this resolved or are there 
> still
> open questions?
> 
> Thanks,
> 
> Steve
> 

Hi Steve,

The PCIe test code is being put on github at: 
https://github.com/intel-hw-ci/Intel-Openstack-Hardware-CI/tree/master/pci_testcases
 
We would readily welcome some feedback if folks think it should go elsewhere, 
but for now the tests are publically available and we can continue to make 
progress.

Regards,
Adrian

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