Hi Felix at this stage I have had no luck getting eth1 to work so I have deliberately left out all the code attempting to make eth1 work. (I am intending to post my progress to my github but I am all coded out for tonight)
But again, having no other point of reference I traced through the working DDWRT driver and discovered that eth1 in this board is connected to S26 internal switch and sends mdio commands over 0x1a000000. An easy test is when the following is present in the mach-dir632-a1.c, and if you add debugging printks into the right places in ag71xx, you can see the kernel enumerating phys 0..8 and 18 in eth0 and phys 0..4 in eth1 and ag71xx_mdio.1.00 --> 05 shows up in /sys/class/mdio + ath79_register_mdio(1, 0); + ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; When I printk instrument the DD-WRT driver you can also see it writing to the mdio registers on 0x1a000000 for eth1 I am new to how kernel ethernet drivers work so it is quite possible I am misunderstanding something or misinterpreting some output - and it is hard to find decent documentation on how all this works other than tracing kernel code and experimenting, and reading and instrumenting the working source code in DD-WRT. --Andrew On 14/05/13 22:39, Felix Fietkau wrote: > On 2013-05-14 2:30 PM, Andrew McDonnell wrote: >> >> This patch allows a board to enable the mdio bus on the second ethernet port >> provided by the AR7242 (as used in the D-Link DIR-632-A1.) The AR7242 (at >> least on the dir632) has two ethernet, eth0 at 0x19000000 and eth1 at >> 0x1a000000, and both have enumerable mdio busses. >> >> It further defaults to connecting eth1 to ag71xx-mdio.1 when registering eth1 >> with ath79 platform data. >> >> Please note this superseded prior email with missing subject(!) > Are you sure about this? In other AR724x SoCs one MDIO bus goes to the > built-in switch, and the other one is external. You don't seem to make > use of the second MDIO bus in your DIR-632-A1 patch either. > I think the AR7242 does not have the built-in switch, so it would > surprise me to see a second MDIO bus being used there. > > - Felix > _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/mailman/listinfo/openwrt-devel
