Hi Felix, I was wondering why there was something out on 18...
if setting that to the phy mask makes everything work after all my debugging I will be very annoyed at myself for not posting my work sooner (and at DD-WRT!) Yes, this patch is not immediately needed for support for the rest of the DIR632 thanks again --Andrew On 14/05/13 23:03, Felix Fietkau wrote: > On 2013-05-14 3:22 PM, Andrew McDonnell wrote: >> Hi Felix >> >> at this stage I have had no luck getting eth1 to work so I have deliberately >> left out all the code attempting to make eth1 work. (I am intending to post >> my progress to my github but I am all coded out for tonight) >> >> But again, having no other point of reference I traced through the working >> DDWRT driver and discovered that eth1 in this board is connected to S26 >> internal switch and sends mdio commands over 0x1a000000. >> >> An easy test is when the following is present in the mach-dir632-a1.c, and if >> you add debugging printks into the right places in ag71xx, you can see the >> kernel enumerating phys 0..8 and 18 in eth0 and phys 0..4 in eth1 and >> ag71xx_mdio.1.00 --> 05 shows up in /sys/class/mdio >> >> + ath79_register_mdio(1, 0); >> + ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; >> >> When I printk instrument the DD-WRT driver you can also see it writing to the >> mdio registers on 0x1a000000 for eth1 >> >> I am new to how kernel ethernet drivers work so it is quite possible I am >> misunderstanding something or misinterpreting some output - and it is hard to >> find decent documentation on how all this works other than tracing kernel >> code >> and experimenting, and reading and instrumenting the working source code in >> DD-WRT. > With DD-WRT you have to keep in mind that it does not have proper > hardware/platform detection in the kernel. It simply registers a whole > bunch of stuff and then tries to fix up the mess in user space. You > should not use its register writes as a reference of what to do. > As for the changes enabling the second MDIO bus - I think we should hold > those back. It's more likely that your board shares the primary MDIO bus > between eth0 and eth1. You could try setting the PHY mask to BIT(18) for > eth1 (using mdio0) to make it attach to that PHY. > > - Felix > _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/mailman/listinfo/openwrt-devel
