On Thu, Jul 4, 2013 at 7:32 PM, Drasko DRASKOVIC <[email protected]> wrote: > Hi Jon, > > On Fri, Jul 5, 2013 at 12:35 AM, [email protected] <[email protected]> > wrote: >> On Tue, Apr 16, 2013 at 6:32 PM, Drasko DRASKOVIC >> <[email protected]> wrote: >>> Hi Jon, >>> both RT3050 and RT5350 have MIPS 24Kc core. I have successfully used >>> OpenOCD with similar (not exactly these) chips, having the same MIPS >>> core. >>> >>> You should use MIPS 4K as a target. >> >> I've bricked one of my AsiaRF modules and I'm trying to recover it. >> >> For some reason reads over my JTAG are painfully slow. Writes as quick. >> >> Takes 20 seconds.... >> mdw 0x80000198 200 >> >> Instant... >> mww 0x80000198 200 0 >> >> Because reads are terribly broken it take 15 minutes to load uboot >> into RAM since OpenOCD verifies the write. >> >> Any idea why reads are so slow? > > Checkout FASTWRITE property of EJTAG, i.e. look in > mips_m4k_read_memory() and see if mips32_pracc_read_mem() gets called > and debug around that. > > Timestamp in wait_for_pracc_rw() to see if you are waiting too long > for READY bit of EJTAG to gets set... > > You cantake a look at the doc > http://repo.or.cz/w/openocd.git/blob/00d6925b41690df17f81ab3da2f37829d7095e19:/doc/manual/target/mips.txt > to understand a bit how it works... > > >> #jtag_speed >> adapter_khz 2000 > > Try playing with adapter_khz. From my point of view this can be fast > for a start, especially if JTAG is unstable. > > Try lowering it to 200 for example, suprisingly you might get better > results... Then try to augment it to see how fast you can go. > > >>> >>> At the time I used it extensively I tried to demystify a code that was >>> there and the code I contributed, so I crafted a doc that you can >>> refer to if you are stuck : http://openocd.zylin.com/#/c/904/ (I am >>> sending you a link to the patchset, although it should be merged in >>> the main tree. However, I do not see it there : >>> http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd;a=tree;f=doc/manual;h=8a9121ca13b9286d258a420f4e301b84bad287b7;hb=08ddb19fd3a708d21057c88e8b86215e04c781ec) >>> >>> Anyway, I can confirm that I was capable to load and JTAG debug both >>> low-level code and Linux, having FASTWRITE and I even added >>> coprocessor manipulations from command line (I added this for correct >>> cache handling, so now both soft and hard breaks should work fine). >>> >>> I am very interested to see how this Chinese TOPLINK story develops. >>> Please keep us informed. >> >> I have the Toplink boards, but I am not so convinced that Toplink >> wants to be in the module business. >> >> I also have the AsiaRF AWM002. AsiaRF is much more interested is >> getting OpenWRT going on their stuff. >> http://www.asiarf.com/Smallest-Tiny-Ralink-802-11n-Wireless-AP-Router-Module-Board-AWM002-product-view-375.html >> >> With 32MB/8MB the modules are around $8.50 Q1000. > > This is very nice price, but I guess that is 8MB, and it will be more for > 32MB.
32MB memory, 8MB flash. If you need 32MB flash they will pass along for whatever the difference is in chip price. > >> AsiaRF will sell Q1 >> for $15 and a dev carrier board for $30. Dev board exposes JTAG, both >> UARTS, two Ethernet and USB. > > Fot this price I would actually rather look at Carambola 2, which can > be bought in 1 unity for 15 eur, around 30 eur for a devboard. Plus > you get Atheros and working SDK. I'm starting to discover some the missing pieces in Ralink support. Like no WifiDirect and no simultaneous (adhoc, AP). Looking at the Ralink driver I don't see why they couldn't be added, but why isn't Ralink doing the work? I have found three AR9331 modules in the $10-12 range. But they are all castellated, I would rather have one with pins. Any idea on the Q1000 price for Carambo2 without VAT? Camabola2 is kind of big for our needs, we like the RT5350 modules since they are putting chips on both sides of the board. That allows them to be much smaller. > > BR, > Drasko -- Jon Smirl [email protected] _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/mailman/listinfo/openwrt-devel
