From: Stewart Hildebrand <[email protected]> Committer: Waldemar Kozaczuk <[email protected]> Branch: master
Cadence: add barrier During early boot, we don't have a good way to map the UART page as Device-nGnRnE memory. I'm testing this on a hypervisor that maps the UART page as Device-GRE memory in the 2nd stage translation table. The OSv early page tables map everything as normal memory in stage 1. As a result, there will be missed characters during early boot, and the OSv version message will appear garbled. After the memory barrier is introduced, OSv prints the proper early version message. The UART page does eventually get mapped as Device-nGnRnE memory, but not until later in the boot process when we switch over to the runtime page tables. Signed-off-by: Stewart Hildebrand <[email protected]> Message-Id: <[email protected]> --- diff --git a/drivers/cadence-uart.cc b/drivers/cadence-uart.cc --- a/drivers/cadence-uart.cc +++ b/drivers/cadence-uart.cc @@ -138,6 +138,9 @@ void Cadence_Console::write(const char *str, size_t len) { asm volatile("nop"); } uart->fifo = *str++; +#ifdef __aarch64__ + asm volatile("dmb nshst"); +#endif len--; } } -- You received this message because you are subscribed to the Google Groups "OSv Development" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/osv-dev/000000000000d04e6205bd816123%40google.com.
