Okay,
With regard to the speed loss that is occuring over power cycles on the T3,
I've performed some experiments to try and isolate the cause, and sadly I've
been unable to do so as yet. I thought some of you might find the results
interesting anyway and can draw your own conclusions...
The first thing I did was try to see if there was any change in the LCD
configuration before and after a power cycle when the T3 was in a freshly
reset mode. I recorded the values of all the LCD configuration registers
before the power cycle and then compared them to the after-cycle values.
There was no significant change in any of the registers.
I tried the same thing with the memory controller and the OS timer and pulse
width modulator registers. Same result...
Since these test didn't reveal the cause of the slowdown, I tried a slightly
different tack. I created the following extremely complex armlet [ ;-) ] as
a direct test of the processor speed:
UInt32 ARMlet_Main(const void *emulStateP, UInt8 *userData68KP,
Call68KFuncType *call68KFuncP)
{
UInt32 x,tval1,tval2;
volatile UInt32 *treg;
treg = (volatile UInt32*)0x90A00010;
tval1 = *treg;
for (x=0;x<1000L;x++) { } // simple delay loop
tval2 = *treg;
return tval2-tval1;
}
I turned off all optimizations so CW9.2 wouldn't optimize away the delay
loop. The register at 0x90A00010 is the OS timer counter and runs at 3.6864
MHz. The following results using this armlet over multiple passes were
observed:
Freshly Reset T3: 29, 29, 29, 29, 29, 29, 28, 29, 29, 29 ...
T3 after Power cycle: 29, 29, 44, 45, 233, 44, 229, 29, 29, 44 ...
The results above are fairly intriguing in that 29 counts of the 3.6864 MHz
counter is approximately 7.9 microseconds, which should be small enough to
fit in a single OS time slice.
I invite your comments and interpretation...
-Robert
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