---Let me guess: Jeff's been to college-and more than
just a day!


 Fluxstringer <[EMAIL PROTECTED]> wrote:
> >>From: "Terry Mathews" <[EMAIL PROTECTED]>
> >>Subject: Re: How to rate one's bus speed?
> >>Date: Thu, 24 Jul 2003 22:58:27 -0400
> >>
> >>>  But I will bow to the experts. My machines must
> run under different
> >>
> >>For whatever reason, all the processor cards you
> tried must have utilized
> >>the same or similar clock speeds. Believe it or
> not, the processor card
> >>tells the motherboard what clock speed to run at.
> That's why most G3 and G4
> >>ZIF carrier cards have some sort of settings for
> the user to configure.
> >
> >To elaborate a bit on what Terry wrote---he's
> absolutely correct. 
> >The memory bus speed on the x500 and x600 (and
> related clones) 
> >machines is set by the CPU card.
> >
> >There is no oscillator on the motherboard which
> provides a 
> >memory/CPU bus clock.  There's an oscillator
> (33.3333) for the PCI 
> >bus, and one for the sound circuitry and one for
> some of the other 
> >I/O, but none for the memory bus.
> >
> >Pins 9 through 14 in the CPU slot connector provide
> the memory/CPU 
> >bus clock signals.   Those signal originate on the
> CPU card, go 
> >through pins 9 through 14 on the CPU connector and
> tell the 
> >components on the motherboard what the bus speed is
> for the CPU card 
> >that is installed.
> >
> >There are six of them because the signals are not
> split.  It's one 
> >clock signal per component.   So one of them goes
> to the memory 
> >controller chip (343S1190), one goes to the PCI
> controller chip 
> >(343S0020) and I'm not sure where the other four
> go.  In the 9500 
> >and 9600 one would go to the other PCI controller
> chip.  In the 7300 
> >- 8600 one would go to the video controller chip
> called 
> >CHAOS/Control. Two may go to the Data Path
> controller (343S1141) but 
> >I'm not certain about that and I've never traced it
> out.   I'm 
> >pretty sure there is at least one and maybe two
> extras that don't 
> >actually go anywhere.
> >
> >Apple originally intended this architecture to be
> capable of 
> >supporting up to four "bridges" on the CPU bus.   
> That would mean 
> >four Bandit chips running twelve PCI slots, or
> three bandit chips 
> >and one built in video, etc.    But they never went
> beyond two in 
> >any machine.
> >
> >Jeff Walther
> 
> 
> Thanks, Jeff that's the clearest elucidation yet on
> this subject. You 
> are an expert.
> 
> >
> 
> -- 
> Adrian
> 
> -- 
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