Indrek Rebane
Thank you for your reply.
That leaves 4 rows/columns on both side. I assume 2 signal layers would not be enough, but 4 sounds reasonable. Now as I do not know anything about power requirements, I can't say anything about power plane needs. One voltage level? Three? Frequency range and current consumption and thus required PDS impedance play role. Vias for PDS are also constraints for routing. If controlled impedance is required then dependent on power planes and layer stackup some additional constraints are set, mainly on width of traces on specific layers.
There is two voltages - 3.3V and 1.5V. Frequency is from 66MHz to 200MHz.
Only a few signals require impedance correspondence. I plan to use 0.1mm line width and 0.1mm clearance.
2)The ball size given by the chip manual is 0.5mm. I want to let the land size be 0.4mm to left more space to place vias and tracks among the pins. In your experience, will there be any problem in installing BGA chip?
IPC-SM-782A section 14.0, Table 6-2 suggests nominal land diameter for 0.5mm ball to be 0.4mm, and range to be 0.35-0.45mm. Upcoming IPC-7351, that will supersede IPC-SM-782A, will suggest land size of 0.45mm however. Both of those are for non-soldermask defined land patterns.
Ideal would be case (for maximum reliability) where pad size and type is equal to pad size on BGA package - left unspecified by many vendors.
Also note that there is quite a nice tool called IPC-7351 land pattern
calculator available from http://pcblibraries.com/ for bargain price
(57USD). You can get 30-days demo of more advanced version from their site.
Sorry. I donot know about IPC-SM-782A section 14.0. How to get it?
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