Actually JaMi if you change the poly display to draft you can see that they
are edge to edge tracks.

Ian Capps
----- Original Message ----- 
From: "JaMi Smith" <[EMAIL PROTECTED]>
To: "Protel EDA Discussion List" <[email protected]>
Sent: Tuesday, March 01, 2005 10:02 AM
Subject: Re: [PEDA] Polygon Pour Problem (& do you know about this bug!?)


> Actually I believe that it is just defaulting to a solid pour, and I am
not quite
> sure whether it is just pouring edge to edge, as someone else mentioned,
or whether
> it is doing a minimum overlap of one of two mils (could always find out by
doing a
> small polygon and then "releasing" it and then looking at the individual
elements
> and their locations).
>
> Even when grid is set to zero, I believe the pour is still made according
to the
> track width that you selected, which will still dictate the resolution
(along with
> smallest segment), which seems to be the deciding factor when it comes to
the actual
> size of the polygon by virtue of the number of elements in the pour.
>
> Now if setting the grid to zero would just  fix the @#*&%$! Analyzing GND
issue . .
> .
>
> JaMi
>
>
>
> ----- Original Message -----
> From: "Terry Creer" <[EMAIL PROTECTED]>
> To: "'Protel EDA Discussion List'" <[email protected]>
> Sent: Monday, February 28, 2005 2:00 PM
> Subject: RE: [PEDA] Polygon Pour Problem (& do you know about this bug!?)
>
>
> > Ok - this is bizarre - I just tried that on a 800+kb PCB file with 2
large
> > polygons - I changed the grid size to zero and it made the final PCB
size
> > 20kb SMALLER.
> >
> > Must be an 'undocumented feature' methinks...
> >
> > TC
> >
> > -----Original Message-----
> > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On
> > Behalf Of Brooks,Bill
> > Sent: Tuesday, 1 March 2005 6:06 AM
> > To: 'Protel EDA Discussion List'
> > Subject: RE: [PEDA] Polygon Pour Problem (& do you know about this
bug!?)
> >
> > Doesn't that make your file size very large?
> > Or is this one of those 'undocumented features'?
> >
> >
> > Bill Brooks - KG6VVP
> > PCB Design Engineer , C.I.D.+, C.I.I.
> > Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
> > e-mail:[EMAIL PROTECTED]
> > http://www.dtwc.com
> > http://pcbwizards.com
> >
> > -----Original Message-----
> > From: Jim Parr [mailto:[EMAIL PROTECTED]
> > Sent: Monday, February 28, 2005 1:36 AM
> > To: Protel EDA Discussion List
> > Subject: Re: [PEDA] Polygon Pour Problem (& do you know about this
bug!?)
> >
> > Hi Brad,
> >
> > >> Oh one tip for you, if you set your polygon grid size to
> > >> "0", it will pour the track widths edge to edge every
> > >> time giving you a solid polygon regardless of the track width.
> >
> > Oh! Very COOL - Haven't figured that in over 5 years! Have just checked
this
> > on 99SE and it works just fine.
> >
> > The artwork I used to test your 'tip' uses some fine dimensioning and
> > pad/component placement.  The outer limits of polygon pours were
previously
> > rather ragged in various places.
> >
> > Your 'tip' completely cleaned up these areas with no other changes.
> >
> > Regards,
> > Jim Parr
> >
> >
> >
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