Igor
From: "Terry Creer" <[EMAIL PROTECTED]> Reply-To: Protel EDA Discussion List <[email protected]> To: "'Protel EDA Discussion List'" <[email protected]> Subject: RE: [PEDA] Polygon Pour Problem (& do you know about this bug!?) Date: Tue, 1 Mar 2005 08:30:53 +1030
Ok - this is bizarre - I just tried that on a 800+kb PCB file with 2 large polygons - I changed the grid size to zero and it made the final PCB size 20kb SMALLER.
Must be an 'undocumented feature' methinks...
TC
-----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Brooks,Bill Sent: Tuesday, 1 March 2005 6:06 AM To: 'Protel EDA Discussion List' Subject: RE: [PEDA] Polygon Pour Problem (& do you know about this bug!?)
Doesn't that make your file size very large? Or is this one of those 'undocumented features'?
Bill Brooks - KG6VVP PCB Design Engineer , C.I.D.+, C.I.I. Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 e-mail:[EMAIL PROTECTED] http://www.dtwc.com http://pcbwizards.com
-----Original Message----- From: Jim Parr [mailto:[EMAIL PROTECTED] Sent: Monday, February 28, 2005 1:36 AM To: Protel EDA Discussion List Subject: Re: [PEDA] Polygon Pour Problem (& do you know about this bug!?)
Hi Brad,
>> Oh one tip for you, if you set your polygon grid size to >> "0", it will pour the track widths edge to edge every >> time giving you a solid polygon regardless of the track width.
Oh! Very COOL - Haven't figured that in over 5 years! Have just checked this
on 99SE and it works just fine.
The artwork I used to test your 'tip' uses some fine dimensioning and pad/component placement. The outer limits of polygon pours were previously rather ragged in various places.
Your 'tip' completely cleaned up these areas with no other changes.
Regards, Jim Parr
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