Dean,
Without knowing how it may effect things on the rest of the design, you
could move your keepout to any distance outside of the board outline. Then set
a clearance rule using Object Type - Keepout and some suitable spacing to the
point at which you want to constrain things inside the board outline. You could
set Scope B to a different object type to control the clearance to any number
of different objects. For your pads near the board outline you could use a
Scope B of Pad Class or some other manner of defining just those pads that are
closer.
Using Object Type - Keepout is no different for layer specific keepouts
or keepout layer objects.
Sincerely,
Brad Velander
Senior PCB Designer
Northern Airborne Technology
1925 Kirschner Rd.,
Kelowna, BC, V1Y 4N7.
tel (250) 763-2329 ext. 225
fax (250) 762-3374
-----Original Message-----
From: Nukien [mailto:[EMAIL PROTECTED]
Sent: April 4, 2005 3:39 PM
To: Protel EDA Discussion List
Subject: [PEDA] How to set clearance constraint for pads close to
keepoutlayer
Hi again -
This is with P99SE-SP6. Take a look at the image (if it comes though that
is). I have a power connector that needs to mount very close to the edge of
the pcb. So much so that one of the plastic guide pins on it will actually
be right on the edge, and two of the pads will be touching the keepout layer
line.
In the pic, the colors are :
Beige - Faceplate position
Dark purple - PCB outline
Bright green - Keepout layer highlighted by clearance constraint violation
The only violation being generated is a clearance constraint between pad J1
and the track on the keepout layer. It's actually touching the keepout
layer track ...
I can't seem to get a clearance constraint rule that will allow this just
for the one J1 component. The keepout layer isn't a choice in the rules,
and I don't want to set the clearance to 0, or the polygon fills will touch
the pad I think.
--
Dean Carpenter
deano at areyes com
94TT :)
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