On 03/16/2011 10:09 PM, 陳韋任 wrote: > Hi, > >> In summary, except for cycles you should do not expect profiles to point at >> instructions that generated the occurrences of the sampling event. > > Even "instructions" event has the skid? > > Regards, > chenwj >
Hi chenwj, The performance monitoring hardware unit on most processors is separated from the the execution part of the processor. Thus, for regular performance monitoring uniting counting events the actual instruction that caused the counter to roll over and trigger the interrupt has long been retired by the time that the processor receives the interrupt from the performance monitoring unit. The interrupts from the performance monitoring unit are not like a trap created by a page fault or divide by zero. The logic to make the performance monitoring precise in the same way as page fault or divide by zero traps is expensive and can slow things down. There are some mechanism such and Intel's Precise Event Buffer (PEBS) and AMD's Instruction Based Sampling to better match events and the instructions that caused them. Depending which processor and version of software you are using these mechanisms might available. -Will ------------------------------------------------------------------------------ Colocation vs. Managed Hosting A question and answer guide to determining the best fit for your organization - today and in the future. http://p.sf.net/sfu/internap-sfd2d _______________________________________________ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
