On Mon, 21 Oct 2013, Stephane Eranian wrote:
> Thanks for the patch. Some comments below.
> I am surprised by the limited number of events
> available.....
I think the eventual plan is that the arm64 events listed are a core set
that most processors will support (there's a defined set that all must
have). Then implementations are free to add other ones.
This code was based off of the manuals and simulator, not real hardware,
so I'm not sure which events a real chip will have.
> > + PFM_PMU_ARM64_ARMV8_PMUV3, /* ARM64 armv8 */
> > +
> Why do we need the PMUV3 suffix here and elsewhere in the patch?
That's how the documentation describes it. (It's an ARMv8 CPU but
an implementation of the PMUv3 PMU spec).
I was naming it sort of
similar to the existing
./lib/pfmlib_arm_armv7_pmuv1.c
> > + {.name = "L1I_CACHE_REFILL",
> > + .modmsk = ARMV7_A15_ATTRS,
>
> Define a new macro to have a clean separation: ARMV8_ATTRS
OK.
Vince
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