On 10/18/2013 03:30 PM, Vince Weaver wrote: > > The following patch adds support for arm64 to libpfm4. > > I was unsure of the naming, currently it's "armv8_pmuv3" which is > a bit awkward.
Yes, armv8_pmuv3 seems a bit verbose. The kernel has similar naming in arch/arm64/kernel/perf_events.c Would it be sane just to group arm performance counters as arm_pmuvN, where N is 1, 2, or 3? > > I also have given some things ARM64 prefixes, but maybe that is > unnecessary and it should just be grouped with the regular ARM files. > I'm not sure what happens to the perf-counters if you run a 32-bit > kernel on an aarch64 device. > > I've test built this on the Foundation simulator but don't have access to > real hardware. I don't have access to hardware either. > > Signed-off-by: Vince Weaver <vincent.wea...@maine.edu> > > diff --git a/config.mk b/config.mk > index 6c010c0..3f6483c 100644 > --- a/config.mk > +++ b/config.mk > @@ -149,6 +149,10 @@ ifeq ($(ARCH),arm) > CONFIG_PFMLIB_ARCH_ARM=y > endif > > +ifeq ($(ARCH),aarch64) > +CONFIG_PFMLIB_ARCH_ARM64=y > +endif > + > ifeq ($(ARCH),s390x) > CONFIG_PFMLIB_ARCH_S390X=y > endif > diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h > index 89b9fd8..41adf03 100644 > --- a/include/perfmon/pfmlib.h > +++ b/include/perfmon/pfmlib.h > @@ -192,6 +192,8 @@ typedef enum { > > PFM_PMU_POWER8, /* IBM POWER8 */ > > + PFM_PMU_ARM64_ARMV8_PMUV3, /* ARM64 armv8 */ > + > /* MUST ADD NEW PMU MODELS HERE */ > > PFM_PMU_MAX /* end marker */ > diff --git a/lib/Makefile b/lib/Makefile > index 98411b8..2411db9 100644 > --- a/lib/Makefile > +++ b/lib/Makefile > @@ -132,6 +132,17 @@ SRCS += pfmlib_arm.c pfmlib_arm_armv7_pmuv1.c > pfmlib_arm_armv6.c > CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM > endif > > +ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y) > + > +ifeq ($(SYS),Linux) > +SRCS += pfmlib_arm_perf_event.c > +endif > + > +INCARCH = $(INC_ARM64) > +SRCS += pfmlib_arm.c pfmlib_arm64_armv8_pmuv3.c > +CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM64 > +endif > + > ifeq ($(CONFIG_PFMLIB_ARCH_MIPS),y) > > ifeq ($(SYS),Linux) > diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c > index e810eca..d139862 100644 > --- a/lib/pfmlib_common.c > +++ b/lib/pfmlib_common.c > @@ -161,6 +161,11 @@ static pfmlib_pmu_t *pfmlib_pmus[]= > &arm_cortex_a15_support, > &arm_1176_support, > #endif > + > +#ifdef CONFIG_PFMLIB_ARCH_ARM64 > + &arm64_armv8_pmuv3_support, > +#endif > + > #ifdef CONFIG_PFMLIB_ARCH_S390X > &s390x_cpum_cf_support, > #endif > diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h > index d3ed361..0a7cdb5 100644 > --- a/lib/pfmlib_priv.h > +++ b/lib/pfmlib_priv.h > + {.name = "CHAIN", > + .modmsk = ARMV7_A15_ATTRS, > + .code = 0x1e, > + .desc = "For odd counters, increment for each overflow of preceding > event-numbered counter. For even-numbered counters, no increment" The "CHAIN" event appears to be used to get wider counters from the 32-bit counters availble. However, it doesn't make sense to code the "CHAIN" event in libpfm because the perf interface doesn't have control where to place the counters with the perf interface. "D6.10.5 Required events" section of the aarch64 manual indicates that some of the events may be omitted in some implmentations and "D6.10.6 IMPLEMENTATION DEFINED event numbers" of the aarch manual indicates that some armv8 implmentations may have additional events. Is there some way in libpfm to determine at runtime which specific arm implementation the code is running on and enable/disable certain events? I know that x86 can use the CPUID instruction to get that information. According to the aarch64 machine "G4.4.9 PMEVTYPER<n>, Performance Monitors Event Type Registers, n = 0 - 30" and "I1.2.19 PMEVTYPER<n>_EL0, Performance Monitors Event Type Registers, n = 0 - 30" the event specifier "evtCount" is 10 bits in size. rather than 8 bits for armv7. All of the currentlly listed events for armv8 fit in 8-bit, just thinking need to be careful about this when some implmentation specific events are defined with the upper 2 bits set. -Will ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60135991&iu=/4140/ostg.clktrk _______________________________________________ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel