Vince,
On Mon, Nov 4, 2013 at 6:20 PM, Vince Weaver <vincent.wea...@maine.edu> wrote:
> Hello
>
> here's an updated version of the arm64 patch.
>
> This version does not have any separate "arm64" naming, it just uses
> ARM_ARMv8. In theory you can boot a 32-bit kernel on an armv8 machine
> so the 64-bit distinction isn't needed anyway.
>
> This new patch also specifically targets the ARM Foundation simulator.
> In theory once the Cortex A53 and Cortex A57 documentation is released
> it will be easy enough to add the proper part numbers to the detection
> routines.
>
Those are the events coming from the Simulator only or core architected
events on ARMv8. I could not check on that because ARM manual for
ARMv8 still requires registration. I don't understand why I need to register
to read an architecture manual.
When the Cortex-A* re released, will they have more events or just the
same foundation? In other words, will we have to add another event table
for those or will be simply shared that one?
> Signed-off-by: Vince Weaver <vincent.wea...@maine.edu>
>
> diff --git a/config.mk b/config.mk
> index 6c010c0..cc352ac 100644
> --- a/config.mk
> +++ b/config.mk
> @@ -149,6 +149,10 @@ ifeq ($(ARCH),arm)
> CONFIG_PFMLIB_ARCH_ARM=y
> endif
>
> +ifeq ($(ARCH),aarch64)
> +CONFIG_PFMLIB_ARCH_ARM=y
> +endif
> +
> ifeq ($(ARCH),s390x)
> CONFIG_PFMLIB_ARCH_S390X=y
> endif
> diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h
> index 89b9fd8..716d686 100644
> --- a/include/perfmon/pfmlib.h
> +++ b/include/perfmon/pfmlib.h
> @@ -192,6 +192,8 @@ typedef enum {
>
> PFM_PMU_POWER8, /* IBM POWER8 */
>
> + PFM_PMU_ARM_ARMV8_FOUNDATION, /* ARM64 armv8 Foundation Simulator */
> +
> /* MUST ADD NEW PMU MODELS HERE */
>
> PFM_PMU_MAX /* end marker */
> diff --git a/lib/Makefile b/lib/Makefile
> index 98411b8..262b320 100644
> --- a/lib/Makefile
> +++ b/lib/Makefile
> @@ -128,7 +128,7 @@ SRCS += pfmlib_arm_perf_event.c
> endif
>
> INCARCH = $(INC_ARM)
> -SRCS += pfmlib_arm.c pfmlib_arm_armv7_pmuv1.c pfmlib_arm_armv6.c
> +SRCS += pfmlib_arm.c pfmlib_arm_armv7_pmuv1.c pfmlib_arm_armv6.c
> pfmlib_arm_armv8.c
> CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM
> endif
>
> diff --git a/lib/pfmlib_arm_priv.h b/lib/pfmlib_arm_priv.h
> index ef367b7..227508b 100644
> --- a/lib/pfmlib_arm_priv.h
> +++ b/lib/pfmlib_arm_priv.h
> @@ -86,6 +86,9 @@ extern int pfm_arm_get_perf_encoding(void *this,
> pfmlib_event_desc_t *e);
> #define ARMV7_A15_ATTRS (_ARM_ATTR_K|_ARM_ATTR_U|_ARM_ATTR_HV)
> #define ARMV7_A15_PLM (PFM_PLM0|PFM_PLM3|PFM_PLMH)
>
> +#define ARMV8_ATTRS (_ARM_ATTR_K|_ARM_ATTR_U|_ARM_ATTR_HV)
> +#define ARMV8_PLM (PFM_PLM0|PFM_PLM3|PFM_PLMH)
> +
> static inline int
> arm_has_plm(void *this, pfmlib_event_desc_t *e)
> {
> diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c
> index e810eca..80e5a71 100644
> --- a/lib/pfmlib_common.c
> +++ b/lib/pfmlib_common.c
> @@ -160,7 +160,9 @@ static pfmlib_pmu_t *pfmlib_pmus[]=
> &arm_cortex_a9_support,
> &arm_cortex_a15_support,
> &arm_1176_support,
> + &arm_armv8_foundation_support,
> #endif
> +
> #ifdef CONFIG_PFMLIB_ARCH_S390X
> &s390x_cpum_cf_support,
> #endif
> diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h
> index d3ed361..0ac0ac4 100644
> --- a/lib/pfmlib_priv.h
> +++ b/lib/pfmlib_priv.h
> @@ -287,6 +287,7 @@ extern pfmlib_pmu_t arm_cortex_a8_support;
> extern pfmlib_pmu_t arm_cortex_a9_support;
> extern pfmlib_pmu_t arm_cortex_a15_support;
> extern pfmlib_pmu_t arm_1176_support;
> +extern pfmlib_pmu_t arm_armv8_foundation_support;
> extern pfmlib_pmu_t mips_74k_support;
> extern pfmlib_pmu_t s390x_cpum_cf_support;
>
> diff --git lib/events/arm_armv8_events.h lib/events/arm_armv8_events.h
> new file mode 100644
> index 0000000..7aac1c0
> --- /dev/null
> +++ lib/events/arm_armv8_events.h
> @@ -0,0 +1,189 @@
> +/*
> + * Copyright (c) 2013 by Vince Weaver <vincent.wea...@maine.edu>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> copies
> + * of the Software, and to permit persons to whom the Software is furnished
> to do so,
> + * subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included
> in all
> + * copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> OR IMPLIED,
> + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
> FOR A
> + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
> COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
> AN ACTION OF
> + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH
> THE SOFTWARE
> + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * From Table D6-6 in the ARM Architecture Reference Manual ARMv8
> + */
> +static const arm_entry_t arm_armv8_foundation_pe[]={
> + {.name = "SW_INCR",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x00,
> + .desc = "Instruction architecturally executed (condition check pass)
> Software increment"
> + },
> + {.name = "L1I_CACHE_REFILL",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x01,
> + .desc = "Level 1 instruction cache refill"
> + },
> + {.name = "L1I_TLB_REFILL",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x02,
> + .desc = "Level 1 instruction TLB refill"
> + },
> + {.name = "L1D_CACHE_REFILL",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x03,
> + .desc = "Level 1 data cache refill"
> + },
> + {.name = "L1D_CACHE_ACCESS",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x04,
> + .desc = "Level 1 data cache access"
> + },
> + {.name = "L1D_TLB_REFILL",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x05,
> + .desc = "Level 1 data TLB refill"
> + },
> + {.name = "LD_RETIRED",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x06,
> + .desc = "Load instruction architecturally exexcuted, condition code
> check pass"
> + },
> + {.name = "ST_RETIRED",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x07,
> + .desc = "Store instruction architecturally exexcuted, condition code
> check pass"
> + },
> + {.name = "INST_RETIRED",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x08,
> + .desc = "Instruction architecturally executed"
> + },
> + {.name = "EXCEPTION_TAKEN",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x09,
> + .desc = "Exception taken"
> + },
> + {.name = "EXCEPTION_RETURN",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x0a,
> + .desc = "Exception return instruction architecturally executed
> (condition check pass)"
> + },
> + {.name = "CID_WRITE_RETIRED",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x0b,
> + .desc = "Instruction architecturally executed (condition check pass)
> Write to CONTEXTIDR"
> + },
> + {.name = "PC_WRITE_RETIRED",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x0c,
> + .desc = "Software change of the PC, instruction architecturally
> executed (condition check pass)"
> + },
> + {.name = "BR_IMMED_RETIRED",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x0d,
> + .desc = "Immediate branch, instruction architecturally executed"
> + },
> + {.name = "BR_RETURN_RETIRED",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x0e,
> + .desc = "Proceudre return, instruction architecturally executed
> (condition code check pass)"
> + },
> + {.name = "UNALIGNED_LDST_RETIRED",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x0f,
> + .desc = "Unaligned load or store, instruction architecturally
> executed (condition code check pass)"
> + },
> + {.name = "BRANCH_MISPRED",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x10,
> + .desc = "Mispredicted or not predicted branch speculatively executed"
> + },
> + {.name = "CPU_CYCLES",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x11,
> + .desc = "Cycles"
> + },
> + {.name = "BRANCH_PRED",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x12,
> + .desc = "Predictable branch speculatively executed"
> + },
> + {.name = "DATA_MEM_ACCESS",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x13,
> + .desc = "Data memory access"
> + },
> + {.name = "L1I_CACHE_ACCESS",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x14,
> + .desc = "Level 1 instruction cache access"
> + },
> + {.name = "L1D_CACHE_WB",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x15,
> + .desc = "Level 1 data cache WriteBack"
> + },
> + {.name = "L2D_CACHE_ACCESS",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x16,
> + .desc = "Level 2 data cache access"
> + },
> + {.name = "L2D_CACHE_REFILL",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x17,
> + .desc = "Level 2 data cache refill"
> + },
> + {.name = "L2D_CACHE_WB",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x18,
> + .desc = "Level 2 data cache write-back"
> + },
> + {.name = "BUS_ACCESS",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x19,
> + .desc = "Bus access"
> + },
> + {.name = "LOCAL_MEMORY_ERROR",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x1a,
> + .desc = "Local memory error"
> + },
> + {.name = "INST_SPEC_EXEC",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x1b,
> + .desc = "Operation speculatively executed"
> + },
> + {.name = "TTBR_WRITE_RETIRED",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x1c,
> + .desc = "Instruction architecturally executed (condition check pass)
> Write to translation table base"
> + },
> + {.name = "BUS_CYCLES",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x1d,
> + .desc = "Bus cycle"
> + },
> + {.name = "CHAIN",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x1e,
> + .desc = "For odd counters, increment for each overflow of preceding
> event-numbered counter. For even-numbered counters, no increment"
> + },
> + {.name = "L1D_CACHE_ALLOCATE",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x1f,
> + .desc = "Level 1 data cache allocation without refill"
> + },
> + {.name = "L2D_CACHE_ALLOCATE",
> + .modmsk = ARMV8_ATTRS,
> + .code = 0x20,
> + .desc = "Level 2 data cache allocation without refill"
> + },
> +};
> diff --git lib/pfmlib_arm_armv8.c lib/pfmlib_arm_armv8.c
> new file mode 100644
> index 0000000..d6b708c
> --- /dev/null
> +++ lib/pfmlib_arm_armv8.c
> @@ -0,0 +1,78 @@
> +/*
> + * pfmlib_arm_armv8.c : support for ARMv8 chips
> + *
> + * Copyright (c) 2013 by Vince Weaver <vincent.wea...@maine.edu>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> copies
> + * of the Software, and to permit persons to whom the Software is furnished
> to do so,
> + * subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included
> in all
> + * copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> OR IMPLIED,
> + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
> FOR A
> + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
> COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
> AN ACTION OF
> + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH
> THE SOFTWARE
> + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include <sys/types.h>
> +#include <string.h>
> +#include <stdlib.h>
> +#include <stdio.h>
> +#include <stdarg.h>
> +
> +/* private headers */
> +#include "pfmlib_priv.h" /* library private */
> +#include "pfmlib_arm_priv.h"
> +
> +#include "events/arm_armv8_events.h" /* event tables */
> +
> +static int
> +pfm_arm_detect_armv8_foundation(void *this)
> +{
> +
> + int ret;
> +
> + ret = pfm_arm_detect(this);
> + if (ret != PFM_SUCCESS)
> + return PFM_ERR_NOTSUPP;
> +
> + if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */
> + (pfm_arm_cfg.part == 0xd00)) { /* Foundation Simulator */
> + return PFM_SUCCESS;
> + }
> + return PFM_ERR_NOTSUPP;
> +}
> +
> +
> +/* ARMv8 Foundation Simulator Support */
> +pfmlib_pmu_t arm_armv8_foundation_support={
> + .desc = "ARMv8 Foundation Simulator",
> + .name = "arm_foundation",
> + .pmu = PFM_PMU_ARM_ARMV8_FOUNDATION,
> + .pme_count = LIBPFM_ARRAY_SIZE(arm_armv8_foundation_pe),
> + .type = PFM_PMU_TYPE_CORE,
> + .pe = arm_armv8_foundation_pe,
> +
> + .pmu_detect = pfm_arm_detect_armv8_foundation,
> + .max_encoding = 1,
> + .num_cntrs = 31,
> +
> + .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding,
> + PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding),
> + .get_event_first = pfm_arm_get_event_first,
> + .get_event_next = pfm_arm_get_event_next,
> + .event_is_valid = pfm_arm_event_is_valid,
> + .validate_table = pfm_arm_validate_table,
> + .get_event_info = pfm_arm_get_event_info,
> + .get_event_attr_info = pfm_arm_get_event_attr_info,
> + PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs),
> + .get_event_nattrs = pfm_arm_get_event_nattrs,
> +};
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