On 11/11/2013 01:31 PM, Vince Weaver wrote: > On Mon, 11 Nov 2013, Stephane Eranian wrote: > >>> This new patch also specifically targets the ARM Foundation simulator. >>> In theory once the Cortex A53 and Cortex A57 documentation is released >>> it will be easy enough to add the proper part numbers to the detection >>> routines. >>> >> Those are the events coming from the Simulator only or core architected >> events on ARMv8. I could not check on that because ARM manual for >> ARMv8 still requires registration. I don't understand why I need to register >> to read an architecture manual. > > many of the ARM documents require registration :( Although the > registration process is fairly painless, it's still annoying to have to do > it. > >> When the Cortex-A* re released, will they have more events or just the >> same foundation? In other words, will we have to add another event table >> for those or will be simply shared that one? > > It's unclear, and I personally have no inside knowledge. > > If you look at the kernel driver in arch/arm64/kernel/perf_event.c the > current code is just for generic armv8/pmuv3 (which is more or less what > my patch supports, I test-built in the simulator but the simulator itself > doesn't support counters). The kernel makes no provisions for different > CPUs having different events, but maybe that will change once the -A5* > documentation is released. > > Vince > Hi Stephane and Vince,
I don't have inside knowledge either, but there appears to be some room for implementation specific events. There is a section: "D6.10.6 IMPLEMENTATION DEFINED event numbers" in the AArch64 reference manual that describes creating event for specific implementations. So it looks quite possible that other events may be present. The newer intel processors have architected events and the aarch64 kind of looks like the set in this patch would be pretty similar in scope to the Intel architected events. The "D8.4.3 PMCEID0_EL0, Performance Monitors Common Event Identification register 0" and "D8.4.4 PMCEID1_EL0, Performance Monitors Common Event Identification register 1" of the AArch64 describes a register that shows which events are implements. -Will ------------------------------------------------------------------------------ November Webinars for C, C++, Fortran Developers Accelerate application performance with scalable programming models. Explore techniques for threading, error checking, porting, and tuning. Get the most from the latest Intel processors and coprocessors. See abstracts and register http://pubads.g.doubleclick.net/gampad/clk?id=60136231&iu=/4140/ostg.clktrk _______________________________________________ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
