Yes, the reference design is a large board with all possible associated
components demonstrated and long traces of course.  Trise is 2 nsec.,
(Tprop=138ps/in)., Lcrit=2.4 inches


regards,
Tim Hutcheson
[EMAIL PROTECTED]




> -----Original Message-----
> From: Jon Elson [mailto:[EMAIL PROTECTED]]
> Sent: Monday, August 06, 2001 6:09 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] 5/5 Manufacturing Issues
>
>
>
>
> Tim Hutcheson wrote:
>
> > Cool.  Traces are short, less than 2.5" max, getting shorter as
> I eliminate
> > resistors. :-)
> >
> > Rise time is large, nominally it is 2 nsec.
>
> This should work.  2 nS Tr is pretty generous.  The wavefront
> with a 2 nS Tr
> is about 15" long, so you won't even see the incident wave step.
> I'm a little
> bit surprised the termination is really necessary, unless the
> reference design
> has a LOT longer traces.  My guess is you could use any
> reasonable trace width
> without resistors, and the 50 Ohm drivers will still absorb the transients
> quickly enough to keep the system working correctly.  At 133 MHz (assuming
> single-data rate) the time between clocks is 7.5 nS (although the
> setup and hold
>
> times at the receiving chips are bound to be less).  If this is
> DDR, then it is
> getting
> tight, but I bet it would still work.  There just won't be much of that
> transient
> rattling around on such a short line with a 2 nS Tr (unless that
> is a worst-case
>
> maximum Tr).  Now, if the Tr was 200 pS, it is a whole different story!
>
> Jon

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