Ken Pelic wrote:

>
> Here's the scenario:
>
> In BGAs we have in this design, several pads are not used and therefore
> don't
> have any assigned netnames. We want access to them due to this being an
> initial
> prototype design and so we have vias associated with the pads to provide
> access
> to them even though they are currently unused. In the debug stage, we may
> need
> to make use of them and this provides that access if necessary. Of course,
> everything associated with the unused pads is flagged as a DRC error. My
> desire
> would be to set a design rule where anything associated with these unused
> pads
> is not flagged, but everything else is to prevent missing any real DRC
> errors in
> this design.

What I would do is put into the schematic net names such as spare01, spare02
etc, and treat these as if they were any other signal.  The via could be
replaced
with a single pad component of equivalent pad and hole size, or call it a test
point.
That will get rid of the error message, and the schematic will show the pad and
BGA pin assignment clearly, too.

Jon

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