Hi Florian,

for what do you need teardrops. Do you design single - side boards of FR2
for consumer - products ?

I think there is no sense to do this for plated FR4 boards.

I would be glad to hear about other opinions about that.

Georg



> -----Urspr ngliche Nachricht-----
> Von: Florian Finsterbusch [mailto:[EMAIL PROTECTED]]
> Gesendet: Freitag, 14. September 2001 09:18
> An: Protel EDA Forum
> Betreff: [PEDA] AW: Problems when pouring polygons
>
>
> Hello All,
>
> as promised, i will inform you about the progress with our
> polygon pouring
> problem.
>
> I have send our database-file to the Altium Switzerland
> support center.
> They have checked the file and have given us the following statement:
>
> "I've looked at the polygon board, the problem was related to
> the teardrops.
> Removing them, or changing them from arcs to tracks solved
> the problem..."
> "This issue will be fixed in the next release."
>
> So it is a bug!
> (And i hope, it will really be fixed in the next relaese.)
>
>
> Florian
>
>
> > -----Ursprungliche Nachricht-----
> > Von: Florian Finsterbusch [mailto:[EMAIL PROTECTED]]
> > Gesendet: Donnerstag, 6. September 2001 10:40
> > An: Protel EDA Forum
> > Betreff: [PEDA] AW: Problems when pouring polygons
> >
> >
> > Hello Abd ul-Rahman,
> >
> > thank you for your attempts to solve the mystery of pouring polgons!
> >
> > I have made same tests you have suggested (see below).
> >
> >
> > Florian
> >
> >
> > > -----Ursprungliche Nachricht-----
> > > Von: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
> > > Gesendet: Donnerstag, 6. September 2001 00:05
> > > An: Protel EDA Forum
> > > Betreff: Re: [PEDA] Problems when pouring polygons
> > >
> > >
> > > At 09:56 AM 9/5/01 +0200, Florian Finsterbusch wrote:
> > > >On our multilayer board the top and bottom layer should be
> > > connected to GND.
> > > >For that purpose we have placed polygons on both layers.
> > > >The polygons are connected to the GND net.
> > > >The pads should be surrounded by arcs.
> > > >Grid Size = 0.2 mm, Track Width = 0.22 mm
> > >
> > > First of all, set the grid to zero. I also recommend using
> > imperial units
> > > for the track width, though I am not sure that this will make a
> > > difference;
> > > it's just that the Protel internal database is imperial so you
> > > might get a
> > > slightly better pour.
> > >
> >
> > No cure
> >
> > > >When protel is pouring the polygon, we have rectangles around
> > some pads.
> > > >Also we have rectangular openings in the polygon itself!
> > >
> > > Something like this is to be expected under some
> conditions. For some
> > > reason the pour routine is unable to place the fill
> tracks; if an arc is
> > > missing, any opening left will be rectangular, if one has
> 90 degree
> > > hatching selected. Mr. Finsterbusch did not state his
> setting for the
> > > minimum primitive size. If this is too large there will likely
> > be missing
> > > primitives. This would only get worse with a fixed grid size.
> > >
> > > A minimum length of zero seems to work fine. However, under some
> > > conditions
> > > this could result in too many pour tracks and I would not
> be terribly
> > > surprised if Protel crashed. I leave it at 1 mil. One could make
> > > it smaller
> > > than that.
> > >
> >
> > My minimum primitive size was 3 mils.
> > Changing it to 1 mil makes no difference.
> >
> > > Try setting hatching style to "No Hatching" and turn off
> "Remove Dead
> > > Copper." This will show you only the pad clearance outlines and
> > > the outline
> > > of the polygon. With this setting, polygon pour will surround
> > > each pad with
> > > an arc or octagon (octagons may reduce plot size if software arcs
> > > are used)
> > > *if* the clearance rules will allow it. The grid size has
> no effect on
> > > this. If you are not getting an outline around a pad,
> there are two
> > > possibilities:
> > >
> >
> > Some vias have got no surrounding arcs!
> >
> > > (1) your clearance rules will not allow it.
> > > (2) there is a bug. I think I have seen some circumstances
> > where the pour
> > > outlines are incomplete, but it is difficult to reproduce and I
> > > don't have
> > > an example handy.
> > >
> > > Number (1) is the most likely cause. Try placing a line
> or arc primitive
> > > where you think a missing primitive would be. Assign it the GND
> > net. Does
> > > this create a clearance violation? If so, no wonder the
> pour does not
> > > complete the fill!
> >
> > Placing the arcs manually and assigning them to GND
> produces no clearance
> > violation
> > Because of that i am thinking it is reallay a Protel bug!
> >
> > >
> > > Then, if hatching is turned on, fill track will be added. This
> > > track is *on
> > > grid*. If your grid setting does not meld well with the
> pad placements,
> > > some fill tracks will be missing, causing rectangular holes in
> > your pour.
> > > For this reason, set the grid to zero. Protel properly
> > interprets this as
> > > meaning "fill gridless." This is generally recommended,
> it should be the
> > > default setting!
> > >
> > > There is little reason to use cross-hatching (90 degrees
> or 45 degrees)
> > > when grid is set to zero and a very small primitive length is
> > > used. It will
> > > just add extra lines. Note, however, that lines which are
> > > precisely butted
> > > up next to each other can display a very fine gap, either in PCB
> > > or in some
> > > gerber viewers. That is not real, it is a display artifact. But
> > if one is
> > > not willing to tolerate the appearance of this false gap -- it
> > should not
> > > be on the film -- then using cross-hatching will eliminate it.
> > > That may be
> > > a better solution than using a pour grid and a slightly
> oversize track.
> > >
> > > There are other possible causes for missing track. For example,
> > > there might
> > > be a layer-specific keepout primitive that is invisible, or some
> > > other rule
> > > interaction. Note that there are design rule clearance
> settings for
> > > polygons which are in addition to the other clearance rules. (Most
> > > designers would prefer larger clearances on polygons than
> elsewhere on a
> > > layer because the polygon clearances are everywhere and thus more
> > > likely to
> > > cause fabrication or soldering problems.)
> > >
> > > If the cause of the problem is not found, I recommend creating a
> > > small file
> > > that shows the problem. (Edit down your existing file).
> This will help
> > > Protel, but before sending it to Protel, submit it to me or to
> > > another user
> > > who has indicated a willingness to look at it -- don't attempt
> > to send it
> > > to the list!)
> > >
> > > If there turns out to be a bug here, we can then add this to the
> > > bug database.
> > >
> > > [EMAIL PROTECTED]
> > > Abdulrahman Lomax
> > > Easthampton, Massachusetts USA
> > >
> >
>

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