works also fine in Protel.
G. Auge
"Sean James"
<sjames@telecast- An: "Protel EDA Forum"
<[EMAIL PROTECTED]>
fiber.com> Kopie:
Thema: Re: [PEDA] vias vs. pads
13.11.2001 15:23
Bitte antworten
an "Protel EDA
Forum"
also don't have thermal reliefs like pads. (This works in PCAD,
though).
Sean James
PCB Designer
Telecast Fiber Systems, Inc.
102 Grove Street
Worcester, MA 01605
(TEL) 508.754.4858 x33
(FAX) 413.541.6170
----- Original Message -----
From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Monday, November 12, 2001 11:09 PM
Subject: [PEDA] vias vs. pads
> The differences between vias and free pads are artificial.
>
> Vias in Protel 99SE are essentially free pads with the following
limitations:
>
> (1) Vias cannot have names
> (2) Vias cannot be any shape except circular.
> (3) Vias cannot exist on a single layer only. (I'm not sure about this,
it
> is conceivable that one could configure a buried/blind via with one layer
> only. But my expectation would be that it would not work, or if it
"works"
> it would set up many bugs, being thoroughly unconsidered and untested, I
> would think.
>
> Pads can do all of the above.
>
> on the other side, free pads are vias with the following limitations:
> (1) Free pads cannot be blind or buried, i.e., if they have a hole, it
goes
> all the way through the board.
> (2) If they are in a footprint (i.e., not free) their net assignments are
> affected by netlist load.
>
> Give us blind/buried layer attributes for pads and free pads will do
> everything that vias will do, plus they can be named, which means that it
> is easy to assign special rules to them.
>
> Vias, however, should be maintained for backward compatibility and the
> occasional via that one wants to be part of a footprint -- and/or a way
> should be introduced to cause a pad to behave under netlist load and DRC
> like a via. Perhaps a via checkbox.
> [EMAIL PROTECTED]
> Abdulrahman Lomax
> Easthampton, Massachusetts USA
>
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