At 01:48 PM 1/23/2002 -0500, [EMAIL PROTECTED] wrote:
> > What is generally considered too close of spacing between a through
> hole and
> > an SMT pad?
> >
>
>Anything which doesn't leave some soldermask in between the two, unless
>you're doing some of the more exotic tricks which allow vias in pads.
If the vias are tented, one could put the hole very close, but I'd feel
most comfortable if the via pad does not touch the SMT pad, since solder
could conceivably wick under the solder mask tent. I've used a 5 mil
clearance, via pad to SMT pad.
The issue is especially important because of a desire, with high-speed
design, to make the loop area as small as possible. Putting the vias
inboard (i.e., more toward the center of the part) may improve high speed
performance by reducing loop area.
i.e.
PAD VIA VIA PAD
VIA VIA--------------gnd plane
VIA-------------------power plane
instead of
VIA PAD PAD VIA
VIA VIA----------gnd plane
VIA-----------------------power plane
(The vias would be offset so that they will fit in the space between the
capacitor pads, or they will be to one side of the part.)
From a noise perspective, we would put the vias in the pads, or fully
inboard as in the first example shown above, and I'd think that placing
them close to the center of the part and to each other as possible would be
best.
Blind vias will have little or no problem sucking solder, particularly if
the power layers are just below the surface, so I'd think they could be
placed in pads. Comments?
[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA
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