My alternative for handling tie components would be to allow a flag
to attach to copper placed within a library component. The schematic
component for a net-tie would have two pins as per usual. Then the
PCB component would have two surface pads plus a drawn track or other
primitive which has an embedded flag indicating that it doesn't exist
for DRC short checking.

This solution would allow me to create a library of microstrip features
that could be represented cleanly on the schematic without having to
go through and set up huge numbers of design rules. The Lomax Virtual
Short is great, but unwieldy when putting together RF board designs.

John Haddy

> -----Original Message-----
> From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
> Sent: Friday, 22 February 2002 5:08 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Tie compoents(Ex: RF footprints)
>
>
> At 01:10 PM 2/21/2002 +1100, Ian Wilson wrote:
> >There are a few workarounds.  The one that I think is most documentable
> >but sometimes subject to Gerbering issues is the Lomax Virtual Short.
>
> Note that Lomax himself now considers as at least equally
> satisfactory the
> use of mech layer shorts merged in the gerbers through CAM Manager
> definitions (which can be named, helping with documentation for future
> generations), the shorts being part of a special jumper
> component, just as
> with the virtual short.
>
> Note that Schematic control of the short is a very important part of any
> solution. Schemes which do not automatically create and separate nets
> except at one point, the visible and controllable short between nets, do
> not satisfy this criterion; specifically this would be an
> argument against
> the modification of split planes as some have used.
>
> >Basic method: make a really small gap between two small pads (0.1 mil),
> >give each pad a name and then create a special clearance design rule to
> >allow such a small gap between these pads.  Issues to watch for
> are gerber
> >rounding and aperture matching.  So set a tight apt matching
> tolerance and
> >set gerber to include more than the standard 3 decimal figures.
>
> It is best if the pads in question are part of a jumper which appears on
> the schematic; the whole process becomes automatic at that point. Want a
> single-point ground? Put a single-point ground jumper on the schematic.
> With the virtual short you will need to set a design rule
> allowing the pads
> of that component to be so close to each other; with the mech layer
> solution, you still need to set up a special gerber definition and,
> preferably, to name the mech layer or layers used appropriately.
>
> The gap should be smaller than 0.1 mil in my opinion. I've used 0.002 or
> 0.004 mil. Protel can get a little flaky in the sub-mil region,
> so one may
> need to experiment (examples have been given in the past of sizes and
> definitions known to work).
>
> PCAD has tienet polygons. I consider that solution, as far as I
> understand
> it, as inferior to either of the workarounds we have at present.
>
> I've described in the past various alternatives, I think, as to
> how Protel
> could make this a directly accessible feature, instead of merely a
> workaround. Instead of going down that road again, I'll just state what I
> consider desireable.
>
> I want to place a symbol on a schematic; it may have any number of pins,
> and these pins will be kept separate for netlist generation. However, the
> footprint which is associated with this symbol may have pads which are
> shorted together without creating any DRC error.
>
> This, I think, would actually be quite simple to implement, it is really
> only a little jiggering with the DRC routines. Perhaps the routines would
> recognize something about the name of the symbol, in the type field
> perhaps, since that is fixed to be generated from the symbol name, which
> allows shorts between the nets of the pads to take place within the pad
> areas, whether by the pads themselves shorting or by track
> connected to the
> pads (provided that they only short within the pad area, not anywhere
> else). No special rule should be needed, because it is extra work
> to create
> such a rule and errors may take place during that. More than one name
> should be possible for this symbol, so perhaps the name would have a
> controlled prefix, such as PCBSHORT.
>
> Protel support is distinct from Protel engineering. While we would wish
> that support personnel would read and be familiar with this list, I don't
> think that they are at this time. I might be wrong about that, at least
> with regard to some. I've many times said that it is completely
> natural and
> to be expected that this list can provide better support than Protel; I
> would suggest, in fact, that Protel abandon much of its direct
> support and
> direct the funds freed up by this to software maintenance and
> development.
> Basically, issues that were not resolved quickly on this list
> would then be
> referred to support personnel, who would be very closely connected to
> engineering.
>
> This list generally answers questions more quickly than Protel support
> could possibly manage unless they were to throw a *lot* of money into the
> effort. And that would be silly.
>
> [EMAIL PROTECTED]
> Abdulrahman Lomax
> Easthampton, Massachusetts USA
>

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.html
*
* Contact the list manager:
* mailto:[EMAIL PROTECTED]
*
* Forum Guidelines Rules:
* http://www.techservinc.com/protelusers/forumrules.html
*
* Browse or Search previous postings:
* http://www.mail-archive.com/proteledaforum@techservinc.com
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

Reply via email to