Yes, I would really like a "Tie Net" entity!

Particularly (or most commonly) for the "analog ground" and "digital ground"
situation. I set different nets in the schematic, but when it comes time to
layout the PCB, the DRC spits the dummy when I tie the two grounds together
at the star point.

Does anyone have a work-around for this?
i.e. keep the two grounds (AGND and DGND) separate, EXCEPT for the nominated
tie point

Damon Kelly
Hardware Engineer


> -----Original Message-----
> From: Ian Wilson [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, 21 February 2002 11:25
> To: Protel EDA Forum
> Subject: Re: [PEDA] RF footprints
> 
> 
> On 04:25 PM 20/02/2002 -0800, JaMi Smith said:
> 
> >In view of your understanding of the problem, I take it then that you
> >too agree that there is a need for this issue to be 
> presented to Protel.
> >
> >Really, not ranting,
> >
> >JaMi
> 
> No, but care must be taken with language - mine was carefully 
> chosen to be 
> rude.  I am not sure if you wanted to create the impression of 
> superciliousness but I am afraid that is the impression I 
> took away from a 
> reply that starts:
> 
> >Abdul,
> >
> >Well ~
> >
> >You're almost right . . .
> >
> >A typical RF Choke on a PCB is a certain length conductor 
> (typically 1/4
> 
> (Especially after the last recent round of email designed to 
> goad the only 
> list member who *really* takes that time to understand the 
> subtleties of 
> each persons questions and responses.)
> 
> Anyway on to matters of substance - Yes, I would like a Tie 
> entity that was 
> able to safely control the shorting of nets. This entity should be 
> embeddable in library components as well as be able to be 
> used as a free 
> entity.  It should not constrain us as to what width it has 
> and ideally 
> what shape it can take.  IMO, it should certainly allow for safe net 
> collisions in the following forms:
> 1) track to track  (tracks include arcs)
> 2) track to pad
> 3) track to fill
> 4) fill to fill
> 5) pad to pad may be difficult but may also be a nice feature.
> 
> I would also like the Allow Short Circuits design rule to 
> have region and 
> object scopes.  This has been discussed before.  At the time it was 
> discussed in the manner in which we have found has results 
> with Protel now 
> Altium.  That is constructive discussion about where the flaw 
> maybe and 
> then suggestions for how it can be better.
> 
> Many of us who were part of the debacle of P99 and then the major 
> improvements in P99SE have learnt that cryptic comments like "Go ask 
> Protel" have no beneficial effect.  Much better to present the 
> issue,  state what you would like and then have a calm, warts-and-all 
> discussion.  Protel do watch this list and, I am sure,note 
> when consensus 
> is forming and also, I am sure, go away and think about methods of 
> implementing some of the features that we have not been able 
> to agree on 
> how best to implement.
> 
> Lecture off,
> Ian Wilson
> 

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.html
*
* Contact the list manager:
* mailto:[EMAIL PROTECTED]
*
* Forum Guidelines Rules:
* http://www.techservinc.com/protelusers/forumrules.html
*
* Browse or Search previous postings:
* http://www.mail-archive.com/proteledaforum@techservinc.com
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

Reply via email to