I turn electrical snap off, then set the snap grid to the pitch of the
vias you need e.g. 5mm. Unselect all entities on the board.

I then manually place a full board width row of selected vias (i.e. press
tab before the first via is placed and check the selected flag - then all
subsequent via placements will also be selected), with a unique hole size
if you deem it necessary.

Copy the row of vias and successively paste more rows down the board until
you have a complete matrix.

Do a global edit of selected vias to set the net name e.g. GND

Now the painful part: jump to each DRC error (which will relate to each via
that's been placed on top of a feature attached to another net) and delete
the offending via.

Now the caveat: if you have a via that's landed on a GND net primitive, e.g.
a component land, you won't get a DRC error but you probably won't want a
hole in the pad either.

This is the main reason why I DON'T very often use this method. I find it
better (if annoyingly slow and a good way to get a sore finger from the
mouse clicks) to simply place each via in sequence - which is easy since the
snap grid is set to the pitch desired - making the decision of "to place or
not to place" as I go, based on the surrounding circuitry.

I still make sure I place vias with the selected attribute enabled, so that
I
can easily do a global net assignment without needing to use a unique hole
size.

Hope this helps,

John Haddy

> -----Original Message-----
> From: Sean James [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, 27 February 2002 8:12 AM
> To: Protel EDA Forum
> Subject: [PEDA] VIAS
>
>
> Does anybody know of an easy way to "sprinkle" vias on a board? I want to
> place several (100+) vias on a board to get a good top-bottom current flow
> for GND.
>
> Sean James
> PCB Designer
> Telecast Fiber Systems
> 102 Grove Street
> Worcester, MA 01603
> TEL 508-754-4858 x33
> FAX 413-541-6170
>
>
>
>

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