Hey Gary (et al),

         I've been using Protel to generate JEDECs for GAL16V8's and 
similar for the past year or so without difficulty, though SOME quirkyness 
in getting Protel to process the files and output correctly.

         As an example, the stripped down header from one of my PLD files 
(called 'decoder.pld' inside Protel) looks like this:

/*************************************************************************************/
/*  Advanced PLD99: Schematic to CUPL 
translator                                     */
/*************************************************************************************/
/*  Translated at 
04:50:46                                                           */
/*             on 
20-Nov-2000                                                        */
/*************************************************************************************/
NAME     sigdecoder;
DATE     12/20/2000;
PARTNO   ;
REVISION ;
DESIGNER ;
COMPANY  ;
ASSEMBLY ;
LOCATION ;
DEVICE   g16v8;

         When the PLD file is current focus, PLD->Configure, under the 
'Options' tab, the target device is set to "g16v8", and under the 'Output 
Formats' tab, "JEDEC, POF, PRG" is checked. In this example, lets say your 
.DDB file for the project is saved as C:\GAL16TEST\PROJECT.DDB.  When 
you're in the PLD file inside Protel, you'd select PLD->Compile, and 
hopefully get a 'Complilation Successful' result in the dialog box. Close 
it, and you should shortly get a .REP and .LST file generated and loaded 
onto adjacent 'tabs' to your PLD source file inside the Protel Project.

         In my example, the logic file was called "decoder.pld" - after 
compilation, "decoder.rep" (showing resulting logic and the fusemap) and 
"decoder.lst" (which shows a verbose look at the PLD logic interpreter's 
work on the file - and also any errors appear in here if you don't get a 
successful compilation) should appear and be viewable as plaintext 
documents inside Protel. The JEDEC file output is a bit more confusing, 
though, as most times it never shows up listed *anywhere* in the project. 
In the directory where the .DDB is saved, however, (C:\GAL16TEST in this 
example) you should find the outputted JEDEC text file.

         IMPORTANT NOTE: In this example, the output JEDEC file is called 
"sigdecoder.jed", NOT "decoder.jed" as you might expect. Protel uses the 
"NAME" defining tag in the headers of the PLD to name the JEDEC output 
file, NOT the name of the actual PLD file being compiled. This was a source 
of endless confusion for me at first.

         You should be able to load this resulting JEDEC file into your 
logic programmer of choice, and blast the logic into a chip. As long as 
your PLD sources are correct, you shouldn't have any problems getting it to 
work. After getting over the initial hurdles and hoop-jumping with making 
Protel output the logic, all of the CPLDs I've blasted have resulted in 
exactly what were expected. If you'd like me to send along one of my PLD 
files in it's entirety to test in your setup, let me know. Good luck!!

Regards,
-- Matt


At 09:43 AM 3/9/2002 -0800, you wrote:
>I tried it a couple times and I got output that didn't work. I never had the
>time to review the issue, but I probably should. It generated files, but the
>devices didn't do what I expected. I try the same equations in orcad and the
>device does what I thought it would do.
>
>I'm getting tired of firing up an old copy of Orcad PLD to do it though.
>
>Tony
>
>
>
> > -----Original Message-----
> > From: Gary Packman [mailto:[EMAIL PROTECTED]]
> > Sent: Saturday, March 09, 2002 3:52 AM
> > To: Protel EDA Forum
> > Subject: Re: [PEDA] No JEDEC file from CUPL
> >
> >
> > 3/9/02
> > Thanks for your reply Jeff.  I have tried every combination of
> > boxes checked
> > and unchecked that make sense.  I have G16V8 as the device on my
> > .pld source
> > file and G16V8 as the device type on the options tab.  Also JEDEC
> > under the
> > format hearder on the .pld file.
> >
> > What I expect to see is a text file with a .jed extension along side the
> > .lst, .rep., .SO, .WO output files.  Is this correct?
> >
> > Since I seem to be the only person besides Marcus that has ever had this
> > problem I figure either no one uses CUPL to generate JEDEC
> > programming files
> > or I am doing something wrong.  I suspect the latter.
> >
> > The Protel Knowledge Base gets only three hits using "JEDEC" as the search
> > word, and none of these items shed light on my problem.
> >
> > Any more ideas?  Is there any one out there who is using Protel's CUPL
> > plug-in for actual programming files?
> >
> > I am using 99SE SP6
> >
> > Gary Packman
> >
> >
> >
> > Jeff Stout wrote:
> >
> > > If you are in the Text editor, go to the menu PLD/Configure.../Output
> > > Formats,
> > > and place a check on "JEDEC, POF, PRG".
> > >
> > > Jeff Stout
> > >
> > > ----- Original Message -----
> > > From: "Gary Packman" <[EMAIL PROTECTED]>
> > > To: "PEDA" <[EMAIL PROTECTED]>
> > > Sent: Friday, March 08, 2002 5:16 AM
> > > Subject: [PEDA] No JEDEC file from CUPL
> > >
> > > > 3-8-02
> > > > After successfully compiling and simulating some very simple
> > 16V8 parts
> > > > I cannot get the CUPL compiler to spit out the JEDEC files.
> > I searched
> > > > back to 1999 and found one other question like this posted by Marcus
> > > > Desgronte.  However, there were no responses (at least direct to the
> > > > forum) to his query.
> > > >
> > > > Any similar encounters, suggestions?
> > > >
> > > > Are you still there Marcus?
> > > >
> > > > Please help,
> > > > Gary Packman
> >

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