-----Original Message-----
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, May 21, 2002 4:36 PM
To: Protel EDA Forum
Subject: Re: [PEDA] hidden pin problem

<snip>
I recommend that anyone using the Protel libraries copy the component from 
the lib into their own library and unhide all the hidden pins on all parts 
and the rejig the power pins to either one part having the single set of 
power pins 
<snip>
<snip>
Ian Wilson


I tend to agree with showing all pins and until recently this seemed
straightforward.  For instance, on a dual op-amp package, I would have
visible power pins on the first op-amp and no power on the other op-amp in
the package.  ( this is not without problems - how many times have you been
burned when an op-amp has been rotated to flip the + & - inputs, thereby
putting the negative power rail on top which is usually the positive power
rail... but I digress)
Our department has started using the Simulation and I have had to update our
libraries to support this.  It turns out that an op-amp without any power
pins does not simulate, the Spice netlist builds each op-amp with power pins
for each instance.

Without thinking it through, I popped in some hidden power pins on op-amp B
which made simulation work, but now the PCB netlist suffers from the
'hidden' nets syndrome.  Resulting in two net assignments for the op-amp
power pins!

So it would appear to me that I have to put visible power pins on every
op-amp in a package to make it work for simulation and avoid hidden pin
syndrome.  While this is the lesser of evils, it opens up the possibility of
having different power voltages assigned to the same package.  sigh

Anyone have a more elegant solution?

Duane Foster 

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