Rimas,
        have just a few minutes here to type out a reply, here are my brief
comments.

Your stackup is assymetrical. Your laminate top and bottom should be equal.
An assymmetrical stackup will usually result in unacceptable bow & twist.
Your bottom laminate thickness should match the top 6.3 mil thickness.

Secondly, I would be pretty sure that you can't get core/prepreg in those
precise thicknesses. I don't deal with this a lot but I would be suspicious
about your xx.x mil thicknesses. Have you asked the fabricator what
core/prepreg thicknesses they stock? Use their standard cores/prepregs to
determine the best stackups, then calculate the impedance control trace
widths that you would use/need for your particular impedance.

Third, in your stackup you did not account for copper thickness for your
total stackup thickness. 1/2 oz. CU = 0.7 mil 1 oz. Cu = 1.4mil 2 oz. Cu =
2.8mil.

        Is the thickness of your PCB that critical? Could you get away with
0.055", 0.065", 0.050" or something inbetween. Just asking because that
would give you more leeway in prepreg and core thickness selection.

        Got to run right now. Chat with your fabricator to make sure your
core/prepreg thickness is OK and that they believe your stackup is OK to
fab. Doesn't matter what stackup you create if the fabricator doesn't have
those prepregs or cores to build it with.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com


-----Original Message-----
From: rimas [mailto:[EMAIL PROTECTED]]
Sent: Thursday, August 01, 2002 4:06 PM
To: Protel EDA Forum
Subject: [PEDA] question about layer stackup/controlled impedance
traces...


hello out there,

i'm about to have my first PCB design involving controlled impedance traces 
manufactured in the near future (just a small run of protos).  I only have 
controlled impedance traces on the top layer.  using the transmission line 
impedance calculation tool at:

http://www.eskimo.com/~ultra/calc.htm

(which someone on this list pointed me to before, thanks!)

i've discovered that if I'm using FR4 and 7 mil traces with 2oz of copper, 
that a dielectric width of 6.3 mils will give me a reasonably close 
impedance (52.6 ohms and i'm aiming to get 50)

now here's my question - is this a reasonable way to do the layer stackup? 
(oh yeah, this is a 6 layer board and i'd like the resulting board to be 
.063" wide)

(TOP)
core -> 6.3 mils
prepreg -> 12.6 mils
core -> 12.6 mils
prepreg -> 12.6 mils
core ->  18.9 mils
(BOTTOM)

this seems logical to me but being as that i am inexperienced and such 
things and have noone knowledgeable around here to ask i thought i would 
ask for this group's wisdom.  thanks for any help, hope the 
non-directly-protel related question doesn't bother anyone.

-rimas


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