An unplated hole will give you an incomplete net.  This is usaually not
fatal as you get all your connection holes plated anyway.  I tried several
ways to locate the non-plated items with varying degrees of success.  

-----Original Message-----
From: Robert M. Wolfe [mailto:[EMAIL PROTECTED]]
Sent: Saturday, August 03, 2002 3:08 PM
To: Protel EDA Forum
Subject: [PEDA] 100% complete??????


Hello All,
Anybody run into the Reports vs DRC with respect to 100% complete
connections being different.
I ran DRC for uncomplete net and it is clean 100% connections.
It is a 6 layer card with a split gnd plane, vcc plane not split and there
are many polygon plane 
areas also one layer is mostly polygon planes. I di da very carefull look
there but nothing seems to 
be in error. I also put system in single layer mode and viewed up each layer
to hope to spot a netline,
nothing so far.
If I run the report for connection status I get 1 incomplete net, in this
report it does not tell you the net
that is not connected, unfortunately.
So anybbody got any suggestions as to how to determine if the board is
done??
I did a netlist output from PCB of connected copper, and compared it to the
schematic output netlist and they match 100%.
I also checked for parts off board area by selecting all outside area and
the move slected up and into vieable area and no luck,
I also check Pick and Place for any negative Y coordinates none.
Is there anywhere else to verify 100% completion?
TIA
Bob Wolfe

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