Charlie & all who answered, Thanks. Yes and I actually had 1 smt pad for a new footprint that I actually left unplated somehow, and did in fact find that earlier in the DRC process. However I just found it after much anguish. At least I think this is what happened, somehow (and this part I do not know how or when it happened) but my snap grid got changed to .254mm ( I do all my work in metric). So I re-adjusted that and set my electrical grid to a slighty bigger number and low and behold my last missing connection just went away. I think the grid was changed very late in the design, and the DRC was saying 100%. I did change units once a short time ago just to verify something would that have done it? I have heard that can be risky. So finally I have both reports saying 100% connect status. I was going to let the board go out anyway because I was 99% sure I had no real issues but it is always nice to have your reports come out proper. Thanks for the help Bob Wolfe
----- Original Message ----- From: "Jenkins, Charlie" <[EMAIL PROTECTED]> To: "'Protel EDA Forum'" <[EMAIL PROTECTED]> Sent: Saturday, August 03, 2002 3:37 PM Subject: Re: [PEDA] 100% complete?????? > An unplated hole will give you an incomplete net. This is usaually not > fatal as you get all your connection holes plated anyway. I tried several > ways to locate the non-plated items with varying degrees of success. > > -----Original Message----- > From: Robert M. Wolfe [mailto:[EMAIL PROTECTED]] > Sent: Saturday, August 03, 2002 3:08 PM > To: Protel EDA Forum > Subject: [PEDA] 100% complete?????? > > > Hello All, > Anybody run into the Reports vs DRC with respect to 100% complete > connections being different. > I ran DRC for uncomplete net and it is clean 100% connections. > It is a 6 layer card with a split gnd plane, vcc plane not split and there > are many polygon plane > areas also one layer is mostly polygon planes. I di da very carefull look > there but nothing seems to > be in error. I also put system in single layer mode and viewed up each layer > to hope to spot a netline, > nothing so far. > If I run the report for connection status I get 1 incomplete net, in this > report it does not tell you the net > that is not connected, unfortunately. > So anybbody got any suggestions as to how to determine if the board is > done?? > I did a netlist output from PCB of connected copper, and compared it to the > schematic output netlist and they match 100%. > I also checked for parts off board area by selecting all outside area and > the move slected up and into vieable area and no luck, > I also check Pick and Place for any negative Y coordinates none. > Is there anywhere else to verify 100% completion? > TIA > Bob Wolfe > > ************************************************************************ > * Tracking #: 4D338C446613E74F95209FAD46F9CA2AAB03D873 > * > ************************************************************************ > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
