Hi, Nick.  Yes, I did it ok all on one sheet.  I was trying to see if I
could setup the hierarchical schematic so that both pcb and simulations
could be from one unified set of schematics.  Maybe just dropping in the
sources and loads at the connectors.  Hehe, then I saw how slowly it ran
four just four channels!  We are interested in power behavior and noise
under random conditions.  The design is 6 boards composed of 8 channels each
so it is probably impractical to run a full-ip system simulation anyway but
I think I like to know what the minimum steps needed to do something like
that would be.  So now I can work back in the other direction, hierachically
to see what breaks it.

Thanks for the info.


Tim Hutcheson
Research Associate
Institute for Human and Machine Cognition
University of West Florida
40 S. Alcaniz St.
Pensacola, FL 32501

-----Original Message-----
From: Nick Piccinich [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, August 13, 2002 12:20 PM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] Simulation of multi-channel (sub-sheet) layouts

Hi Tim,

Change your net identifier scope to sheet symbols/port before generating a
new spice (hierarchical) netlist.
If that doesn't work, make the four subsheet schematics with different file
names (change the reference in the sheet symbols in the main sheet, also),
change the netnames/ports to match the main sheet netnames/ports, and rename
the leftover subsheet nets differently.
If this still fails, I would move everything to one page.

Protel tech support told me hierarchical spice is not 100% in Protel 99SE
about a year ago.
It has been improved in DXP, at least for the examples they provide in the
trial version.


-----Original Message-----
From: Tim Hutcheson [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, August 13, 2002 9:17 AM
To: Protel EDA Forum
Subject: [PEDA] Simulation of multi-channel (sub-sheet) layouts

I just tried to simulate a multichannel board composed of a main sheet and 4
subsheets, each a copy of an amplifier connected by the main sheet.  While
the individual amplifier simulates fine (as a separate single sheet
simulation, with source added there) and the .nsx file is generated
perfectly (and inspected carefully) for the active sheet and subsheets, the
simulation quits immediately with no output and no error.  The .sdf is
empty.  The simulation is setup as the simplest AC small signal and
operating point analysis, source is ok, no errors in creation, etc..

Has anyone any experience with this?

thanks in advance.

Tim Hutcheson

* Tracking #: 7A7B5126B37D5E40821AD99D769E3DA5D71D23FE

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