Engineering is the art of compromise. -----Original Message----- From: Danny Bishop [mailto:[EMAIL PROTECTED]] Sent: Friday, 16 August 2002 11:58 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Matched Lenghth Constraint
hmmmm... I guess that kind of goes against the theory that thicker tracks = lower inductance = better immunity... (?) > -----Original Message----- > From: Igor Gmitrovic [mailto:[EMAIL PROTECTED]] > Sent: Friday, 16 August 2002 11:43 AM > To: Protel EDA Forum > Subject: Re: [PEDA] Matched Lenghth Constraint > > > Danny, > > wherever you have a change in the inductance, i.e. track > width, you will get reflections. In such conditions yo could > get standing waves as well, although I don't think that > working frequencies on your board are so high to be affected > by this. Wider track is equivalent to a broadband antenna. It > would then pick up more noise. So you don't really want wider > tracks or variable track width. A good thing to do would be a > short track with as few corners as possible and no vias. To > increase the immunity try shielding the net with a polygon > plane as much as possible. > > Igor > > -----Original Message----- > From: Danny Bishop [mailto:[EMAIL PROTECTED]] > Sent: Friday, 16 August 2002 10:31 AM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Matched Lenghth Constraint > > > Joel > > I appreciate your thoughts, however I don't think I quite got > my reasoning > across as far as my motivation for thinning down a thick > trace in some areas > to fit. In this particular case there is one edge sensitive > net that goes to > 4 logic gates on a board that is otherwise relatively free of critical > traces. My reasoning behind fattening up this trace (to the > point of placing > fills where possible) is to reduce the inductance of the net > where possible > in the hope that it's susceptibility to EMI will reduce. Now > I suppose that > as far as EMI immunity is concerned reflections are less important (?) > particularly considering that this particular signal should > only trigger in > a fault condition and shut down the circuit. > > In a more general case however if this had a clock on it I > wonder if the > introduction of these impedance changes along a trace would > increase or > reduce reliability (particularly with EMI). > > cheers > > > > > -----Original Message----- > > From: Joel Hammer [mailto:[EMAIL PROTECTED]] > > Sent: Friday, 16 August 2002 1:51 AM > > To: Protel EDA Forum > > Subject: Re: [PEDA] Matched Lenghth Constraint > > > > > > Danny, > > I have always been under the belief that if you make a part > > of a trace/track > > thin you might as well make the *entire* trace/track that > > width. (holding > > even more true in power & ground runs. in which case the thin > > run could > > almost act as a fuse.?) If anyone can share logic otherwise I > > would really > > be interested in hearing it. Or am I safe in what I think > to be true? > > > > ----- Original Message ----- > > From: "Andrew Jenkins" <[EMAIL PROTECTED]> > > To: "'Protel EDA Forum'" <[EMAIL PROTECTED]> > > Sent: Thursday, August 15, 2002 10:02 AM > > Subject: Re: [PEDA] Matched Lenghth Constraint > > > > > > > > > > > > > > -----Original Message----- > > > > From: Danny Bishop [mailto:[EMAIL PROTECTED]] > > > >... > > > > I wonder what conclusion we can draw from any potential > > > > benefits of using a thick trace for a tricky trace, but > > > > thinning it down when required to get through tight > > > > spots? > > > > > > I suppose that might depend on how one thins the trace. > > Under certain > > > conditions, I think such a thinning might very well result in an > > > unanticipated reflective interface. That is, if one doesn't take > > UltraCad's > > > analysis as canon, IMO, a safer thinking process than > > simply bleating a > > path > > > to success ;^) > > > > > > aj > > > > > > > > > > > > > > ************************************************************** > > ********** > > > * Tracking #: 74A48E38F8030A4DAB0A361931AAA163D71A3EB1 > > > * > > > > > ************************************************************** > > ********** > > > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
