this is a great picture Ian!
i totally agree with your statements here

we have found the smaller footprints to be both more reliable
and easier to assemble
a large pad deposits more paste than a smaller pad (-duh!)
this, in excess, is one of the main causes of tombstoning

and the huge silkscreen outline accomplishes little
except maybe it makes a tiny profit for ink vendors :)

we have NEVER been able to use protel supplied footprints
for this reason alone

as to maximum packing density:
isn't this a function of the placement jaws?
and isn't that a moving target?

what are good numbers for 0603 for example?
side to side and end to end?

i have no experience w/ SMTPlus
i assume they know what they are doing and i have heard only
good things about them
but since we can't get native protel footprints it greatly 
lessens the appeal for us

when you say wave solder
are you referring to bottom side parts which are glued and
then waved?

regardless of the pad size and in our somewhat limited 
experience with this process (glue, flip and wave)
it has been less satisfactory than a fully reflowed process

Dennis Saputelli

Ian Wilson wrote:
> 
> One to stir up the hornets nest a little...and a little off topic maybe
> 
> http://www.considered.com.au/ProtelFiles/images/Phycomp_vs_IPC.gif
> 
> shows the Phycomp (the old Philips, now part of Yageo) reflow 0402
> footprint versus the 0402 footprint from the Altium P2004 Chip Resistor
> library (in the ../Library/PCB folder) which I think is based on IPC.
> 
> You can see the ridiculous difference.  The one on the left is based on
> reflow with a +/-0.15 mm placement accuracy.  I need maximum packing
> density - IPC in this case is not on for this application.
> 
> The problem with one size fits all (and an oversize like the IPC postage
> stamp footprints) is that assemblers and others can grab onto it as a
> pseudo-standard and say "we only accept IPC footprints".  Instead of
> attempting to understand the pressures on the product and adapting
> processes they simply take the easy way out.  Sure, using small footprints
> may reduce yield and increase costs - in some applications this is
> appropriate.  By *blind* use of overgenerous footprints I think designers
> are loosing the ability to optimise their products globally - they are
> reduced to local optimisation only.  And yes, this is probably a skill that
> is developed over time and with experience - but newcomers to the industry
> should be told, in no uncertain terms, that "IPC footprints are an
> appropriate starting point and since they are designed to cope with many
> soldering processes are necessarily not optimum for any.".
> 
> I am not keen on any library that thinks wave footprints are the same as
> reflow.  Does SMTplus makes the distinction?
> 
> Ian
> 

-- 
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2851 21st Street                    Fax: 415-647-3003
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