http://www.considered.com.au/ProtelFiles/images/Phycomp_vs_IPC.gif
shows the Phycomp (the old Philips, now part of Yageo) reflow 0402 footprint versus the 0402 footprint from the Altium P2004 Chip Resistor library (in the ../Library/PCB folder) which I think is based on IPC.
You can see the ridiculous difference. The one on the left is based on reflow with a +/-0.15 mm placement accuracy. I need maximum packing density - IPC in this case is not on for this application.
The problem with one size fits all (and an oversize like the IPC postage stamp footprints) is that assemblers and others can grab onto it as a pseudo-standard and say "we only accept IPC footprints". Instead of attempting to understand the pressures on the product and adapting processes they simply take the easy way out. Sure, using small footprints may reduce yield and increase costs - in some applications this is appropriate. By *blind* use of overgenerous footprints I think designers are loosing the ability to optimise their products globally - they are reduced to local optimisation only. And yes, this is probably a skill that is developed over time and with experience - but newcomers to the industry should be told, in no uncertain terms, that "IPC footprints are an appropriate starting point and since they are designed to cope with many soldering processes are necessarily not optimum for any.".
I am not keen on any library that thinks wave footprints are the same as reflow. Does SMTplus makes the distinction?
Ian
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