For clearnce setting in PCB design, it will be smaller(eg. 8mil) for normal routing 
while it will be a little larger for polygon objects because that it will increase the 
possibility of short circuit between pad and polygon plane after soldering operation 
if the clearance between polygon and pad is too small.
In the past, I first set a smaller clearance rule for all objects and finish all the 
routing works except pouring polygon plane. And then edit the clearance rule to a 
larger one and pour the polygon. 
Above operation will bring up two problems. First is that after enlarging the 
clearance rule, the routing works before will be found out clearance error by online 
DRC and these error objects will be set to green color. I have to reset these error 
flags. The second problem is that this operation will be some complex when changeing 
the routing work after pouring the polygon.
So I add a new clearance rule from "PCB Rules and Constraints Editor" window via a 
query "IsPolygon". That is to say that at this time, there are at least two clearance 
rules. But the new one does not work! All the polygon pouring work still follows the 
first normal clearance setting. So who can tell me where is wrong. Thank you very much!




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