Hello,

I have a clearance constraint between a trace on the keepout layer and a component on the top layer set to 0mil (I've also tried -1mil) but it still gives me a DRC error between the keepout trace and the component pad that sits on top of it. This is obviously not the correct approach. Suggestions?

Thanks,
Ray Mitchell

Ray Mitchell
Engineer, Code 2732
SPAWAR Systems Center
San Diego, CA. 92152
(619)553-5344
[EMAIL PROTECTED]


* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.html
*
* Contact the list manager:
* mailto:[EMAIL PROTECTED]
*
* Forum Guidelines Rules:
* http://www.techservinc.com/protelusers/forumrules.html
*
* Browse or Search previous postings:
* http://www.mail-archive.com/[EMAIL PROTECTED]
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

Reply via email to