i assume this is near a bd edge?

the bd outline and keepout don't necessarily need to be 
coincident

sometimes we either break the keepout in this situation (if the board is
routed)
or just bend it out a little to make the clearance

negative clearances don't work

Dennis Saputelli


Ray Mitchell wrote:
> 
> Hello,
> 
> I have a clearance constraint between a trace on the keepout layer and a
> component on the top layer set to 0mil (I've also tried -1mil) but it still
> gives me a DRC error between the keepout trace and the component pad that
> sits on top of it.  This is obviously not the correct approach. Suggestions?
> 
> Thanks,
> Ray Mitchell
> 
> Ray Mitchell
> Engineer, Code 2732
> SPAWAR Systems Center
> San Diego, CA. 92152
> (619)553-5344
> [EMAIL PROTECTED]
> 

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2851 21st Street                    Fax: 415-647-3003
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