Hi, On 6/5/25 4:26 AM, taotang2...@gmail.com wrote: > From: Tao Tang <taotang2...@gmail.com> > > The current definition of the SMMU_CR0_RESERVED mask is incorrect. > It mistakenly treats bit 10 (DPT_WALK_EN) as a reserved bit while > treating bit 9 (RES0) as an implemented bit. > > According to the SMMU architecture specification, the layout for CR0 is: > | 31:11| RES0 | > | 10 | DPT_WALK_EN | > | 9 | RES0 | > | 8:6 | VMW | > | 5 | RES0 | > | 4 | ATSCHK | > | 3 | CMDQEN | > | 2 | EVENTQEN | > | 1 | PRIQEN | > | 0 | SMMUEN | > > Signed-off-by: Tao Tang <taotang2...@gmail.com> Reviewed-by: Eric Auger <eric.au...@redhat.com>
Thanks! Eric > --- > hw/arm/smmuv3-internal.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index b6b7399347..42ac77e654 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -120,7 +120,7 @@ REG32(CR0, 0x20) > FIELD(CR0, EVENTQEN, 2, 1) > FIELD(CR0, CMDQEN, 3, 1) > > -#define SMMU_CR0_RESERVED 0xFFFFFC20 > +#define SMMU_CR0_RESERVED 0xFFFFFA20 > > REG32(CR0ACK, 0x24) > REG32(CR1, 0x28)
