On 6/23/25 07:20, Peter Maydell wrote:
On Sun, 22 Jun 2025 at 00:54, Richard Henderson
<richard.hender...@linaro.org> wrote:
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
+static bool do_mova_tile_n(DisasContext *s, arg_mova_t *a, int n, bool to_vec)
+{
+ static gen_helper_gvec_2 * const cz_fns[] = {
+ gen_helper_sme2_mova_cz_b, gen_helper_sme2_mova_cz_h,
+ gen_helper_sme2_mova_cz_s, gen_helper_sme2_mova_cz_d,
+ };
+ static gen_helper_gvec_2 * const zc_fns[] = {
+ gen_helper_sme2_mova_zc_b, gen_helper_sme2_mova_zc_h,
+ gen_helper_sme2_mova_zc_s, gen_helper_sme2_mova_zc_d,
+ };
+ TCGv_ptr t_za;
+ int svl;
+
+ if (!sme_smza_enabled_check(s)) {
+ return true;
+ }
+
+ svl = streaming_vec_reg_size(s);
+ if (svl == 16 && n == 4 && a->esz == MO_64) {
"svl < 32" would be a closer match to the pseudocode.
Exceedingly nitpicky nit: the pseudocode seems to require
that if the SVL is < 256 bits because the implementation
doesn't support any larger SVL then this UNDEF should take
precedence over the SVE/ZA-enabled check, but if the SVL
is < 256 bits because software has set it that way then
that UNDEF check happens after the SVE/ZA-enabled check.
(The former happens in the decode-pseudocode, the latter
in the operation-pseudocode.)
Gotcha. Will fix.
Not all insns seem to have this split. For instance, FEAT_F64MM ZIP[12] w/ Q operands only
has the second operation test.
r~
