There is ongoing effort to run generated test verification on the QEMU riscv CPU which has turned out a few corner cases.
I added some fixes for these, as well as tcg tests. The interrupted vector test also catches a bug in "Generate strided vector loads/stores with tcg nodes." that I referred to in the v5 thread for that series. Thanks, Nick Nicholas Piggin (3): target/riscv: Fix IALIGN check in misa write target/risvc: Fix vector whole ldst vstart check tests/tcg: Add riscv test for interrupted vector ops target/riscv/csr.c | 16 +- target/riscv/vector_helper.c | 2 + tests/tcg/riscv64/Makefile.softmmu-target | 5 + tests/tcg/riscv64/Makefile.target | 10 ++ tests/tcg/riscv64/misa-ialign.S | 88 +++++++++ tests/tcg/riscv64/test-interrupted-v.c | 208 ++++++++++++++++++++++ tests/tcg/riscv64/test-vstart-overflow.c | 75 ++++++++ 7 files changed, 401 insertions(+), 3 deletions(-) create mode 100644 tests/tcg/riscv64/misa-ialign.S create mode 100644 tests/tcg/riscv64/test-interrupted-v.c create mode 100644 tests/tcg/riscv64/test-vstart-overflow.c -- 2.51.0
