According to version 20250508 of the unprivileged specification the frm field of fcsr is 3-bits in size, fix it to 8-bits. Similarly fflags is 5 bits, fix to 8.
Signed-off-by: Anton Johansson <[email protected]> Reviewed-by: Pierrick Bouvier <[email protected]> Acked-by: Alistair Francis <[email protected]> --- target/riscv/cpu.h | 6 +++--- target/riscv/csr.c | 4 ++++ target/riscv/fpu_helper.c | 6 +++--- target/riscv/machine.c | 2 +- 4 files changed, 11 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f00ae69e8a..a55d4ac690 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -231,7 +231,7 @@ struct CPUArchState { /* Floating-Point state */ uint64_t fpr[32]; /* assume both F and D extensions */ - target_ulong frm; + uint8_t frm; float_status fp_status; target_ulong badaddr; @@ -665,8 +665,8 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env, RISCVException exception, uintptr_t pc); -target_ulong riscv_cpu_get_fflags(CPURISCVState *env); -void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); +uint8_t riscv_cpu_get_fflags(CPURISCVState *env); +void riscv_cpu_set_fflags(CPURISCVState *env, uint8_t); FIELD(TB_FLAGS, MEM_IDX, 0, 3) FIELD(TB_FLAGS, FS, 3, 2) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6e7b6d7019..1c6797ca8d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -895,6 +895,10 @@ static RISCVException write_frm(CPURISCVState *env, int csrno, static RISCVException read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { + /* + * This is an 8-bit operation, fflags make up the lower 5 bits and + * frm the upper 3 bits of fcsr. + */ *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) | (env->frm << FSR_RD_SHIFT); return RISCV_EXCP_NONE; diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index af40561b31..db64fca622 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -23,10 +23,10 @@ #include "fpu/softfloat.h" #include "internals.h" -target_ulong riscv_cpu_get_fflags(CPURISCVState *env) +uint8_t riscv_cpu_get_fflags(CPURISCVState *env) { int soft = get_float_exception_flags(&env->fp_status); - target_ulong hard = 0; + uint8_t hard = 0; hard |= (soft & float_flag_inexact) ? FPEXC_NX : 0; hard |= (soft & float_flag_underflow) ? FPEXC_UF : 0; @@ -37,7 +37,7 @@ target_ulong riscv_cpu_get_fflags(CPURISCVState *env) return hard; } -void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard) +void riscv_cpu_set_fflags(CPURISCVState *env, uint8_t hard) { int soft = 0; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 66ed3f6504..07995fb303 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -436,7 +436,7 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINT64(env.pc, RISCVCPU), VMSTATE_UINT64(env.load_res, RISCVCPU), VMSTATE_UINT64(env.load_val, RISCVCPU), - VMSTATE_UINTTL(env.frm, RISCVCPU), + VMSTATE_UINT8(env.frm, RISCVCPU), VMSTATE_UINTTL(env.badaddr, RISCVCPU), VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), VMSTATE_UINTTL(env.priv_ver, RISCVCPU), -- 2.51.0
