Enable the ID_AA64MMFR4_EL1 register, add the ASID2 field for cpu_max, then enable writes to FNG1, FNG0, and A2 bits of TCR2_EL1. Any change of ASID still causes a TLB flush.
Jim MacArthur (3): target/arm: Enable ID_AA64MMFR4_EL1 register. target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 tests: Add test for ASID2 and write/read of feature bits target/arm/cpu-features.h | 7 +++++ target/arm/cpu-sysregs.h.inc | 1 + target/arm/helper.c | 7 +++-- target/arm/tcg/cpu64.c | 4 +++ tests/tcg/aarch64/system/asid2.c | 53 ++++++++++++++++++++++++++++++++ 5 files changed, 70 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/aarch64/system/asid2.c -- 2.43.0
