Tests ASID2 is present and FNG1, FNG0, and A2 are writable, and read value shows the update.
Signed-off-by: Jim MacArthur <[email protected]> --- tests/tcg/aarch64/system/asid2.c | 53 ++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 tests/tcg/aarch64/system/asid2.c diff --git a/tests/tcg/aarch64/system/asid2.c b/tests/tcg/aarch64/system/asid2.c new file mode 100644 index 0000000000..53dbdc13cc --- /dev/null +++ b/tests/tcg/aarch64/system/asid2.c @@ -0,0 +1,53 @@ +/* + * ASID2 Feature presence and enabled TCR2_EL1 bits test + * + * Copyright (c) 2025 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <stdint.h> +#include <minilib.h> + +#define ID_AA64MMFR4_EL1 "S3_0_C0_C7_4" +#define TCR2_EL1 "S3_0_C2_C0_3" + +int main() +{ + /* + * Test for presence of ASID2 and three feature bits enabled by it: + * https://developer.arm.com/documentation/109697/2025_09/Feature-descriptions/The-Armv9-5-architecture-extension + * Bits added are FNG1, FNG0, and A2. These should be RES0 if A2 is + * not enabled and read as the written value if A2 is enabled. + */ + + uint64_t out; + uint64_t idreg; + + /* Mask is FNG1, FNG0, and A2 */ + const uint64_t feature_mask = (1ULL << 18 | 1ULL << 17 | 1ULL << 16); + const uint64_t in = feature_mask; + + asm("mrs %[x1], " ID_AA64MMFR4_EL1 "\n\t" + : [x1] "=r" (idreg)); + if ((idreg & 0xF00) == 0x100) { + /* ASID2 is enabled */ + } else { + ml_printf("FAIL: ASID2 not present in ID_AA64MMFR4 (%lx)\n", idreg); + return 1; + } + + asm("msr " TCR2_EL1 ", %[x0]\n\t" + "mrs %[x1], " TCR2_EL1 "\n\t" + : [x1] "=r" (out) + : [x0] "r" (in)); + + if ((out & feature_mask) == in) { + ml_printf("OK\n"); + return 0; + } else { + ml_printf("FAIL: read value %lx != written value %lx\n", + out & feature_mask, in); + return 1; + } +} -- 2.43.0
