It enables emulation of ECSPI in iMX8MM
Added SPI IRQ lines
Signed-off-by: Gaurav Sharma <[email protected]>
---
docs/system/arm/imx8mm-evk.rst | 1 +
hw/arm/fsl-imx8mm.c | 26 ++++++++++++++++++++++++++
include/hw/arm/fsl-imx8mm.h | 7 +++++++
3 files changed, 34 insertions(+)
diff --git a/docs/system/arm/imx8mm-evk.rst b/docs/system/arm/imx8mm-evk.rst
index 821fd309ec..a7cbb20708 100644
--- a/docs/system/arm/imx8mm-evk.rst
+++ b/docs/system/arm/imx8mm-evk.rst
@@ -16,6 +16,7 @@ The ``imx8mm-evk`` machine implements the following devices:
* 1 Designware PCI Express Controller
* 5 GPIO Controllers
* 6 I2C Controllers
+ * 3 SPI Controllers
* Secure Non-Volatile Storage (SNVS) including an RTC
* Clock Tree
diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c
index 9eb02f0438..a9017c90a0 100644
--- a/hw/arm/fsl-imx8mm.c
+++ b/hw/arm/fsl-imx8mm.c
@@ -192,6 +192,11 @@ static void fsl_imx8mm_init(Object *obj)
object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
}
+ for (i = 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) {
+ g_autofree char *name = g_strdup_printf("spi%d", i + 1);
+ object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
+ }
+
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
object_initialize_child(obj, "pcie_phy", &s->pcie_phy,
TYPE_FSL_IMX8M_PCIE_PHY);
@@ -449,6 +454,26 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error
**errp)
qdev_get_gpio_in(gicdev, usdhc_table[i].irq));
}
+ /* ECSPIs */
+ for (i = 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) {
+ static const struct {
+ hwaddr addr;
+ unsigned int irq;
+ } spi_table[FSL_IMX8MM_NUM_ECSPIS] = {
+ { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI1].addr, FSL_IMX8MM_ECSPI1_IRQ
},
+ { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI2].addr, FSL_IMX8MM_ECSPI2_IRQ
},
+ { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI3].addr, FSL_IMX8MM_ECSPI3_IRQ
},
+ };
+
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
+ return;
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+ qdev_get_gpio_in(gicdev, spi_table[i].irq));
+ }
+
/* SNVS */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) {
return;
@@ -488,6 +513,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error
**errp)
case FSL_IMX8MM_GIC_DIST:
case FSL_IMX8MM_GIC_REDIST:
case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5:
+ case FSL_IMX8MM_ECSPI1 ... FSL_IMX8MM_ECSPI3:
case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4:
case FSL_IMX8MM_PCIE1:
case FSL_IMX8MM_PCIE_PHY1:
diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h
index e68dbd188b..f3a3304565 100644
--- a/include/hw/arm/fsl-imx8mm.h
+++ b/include/hw/arm/fsl-imx8mm.h
@@ -20,6 +20,7 @@
#include "hw/pci-host/designware.h"
#include "hw/pci-host/fsl_imx8m_phy.h"
#include "hw/sd/sdhci.h"
+#include "hw/ssi/imx_spi.h"
#include "qom/object.h"
#include "qemu/units.h"
@@ -31,6 +32,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM)
enum FslImx8mmConfiguration {
FSL_IMX8MM_NUM_CPUS = 4,
+ FSL_IMX8MM_NUM_ECSPIS = 3,
FSL_IMX8MM_NUM_GPIOS = 5,
FSL_IMX8MM_NUM_I2CS = 4,
FSL_IMX8MM_NUM_IRQS = 128,
@@ -47,6 +49,7 @@ struct FslImx8mmState {
IMX8MMCCMState ccm;
IMX8MMAnalogState analog;
IMX7SNVSState snvs;
+ IMXSPIState spi[FSL_IMX8MM_NUM_ECSPIS];
IMXI2CState i2c[FSL_IMX8MM_NUM_I2CS];
IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];
SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];
@@ -175,6 +178,10 @@ enum FslImx8mmIrqs {
FSL_IMX8MM_UART3_IRQ = 28,
FSL_IMX8MM_UART4_IRQ = 29,
+ FSL_IMX8MM_ECSPI1_IRQ = 31,
+ FSL_IMX8MM_ECSPI2_IRQ = 32,
+ FSL_IMX8MM_ECSPI3_IRQ = 33,
+
FSL_IMX8MM_I2C1_IRQ = 35,
FSL_IMX8MM_I2C2_IRQ = 36,
FSL_IMX8MM_I2C3_IRQ = 37,
--
2.34.1
