On 11/20/25 04:54, Jim MacArthur wrote:
This just allows read/write of three feature bits. ASID is still ignored. Any writes to TTBR0_EL0 and TTBR1_EL0, including changing the ASID, will still cause a complete flush of the TLB.Signed-off-by: Jim MacArthur<[email protected]> --- target/arm/cpu-features.h | 7 +++++++ target/arm/helper.c | 6 ++++++ target/arm/tcg/cpu64.c | 4 ++++ 3 files changed, 17 insertions(+)
Reviewed-by: Richard Henderson <[email protected]> r~
