Jim MacArthur <[email protected]> writes: > On Mon, 24 Nov 2025 at 15:01, Alex Bennée <[email protected]> wrote: >> If we instead use this to test for the presence of the feature and then... >> >> > + >> > + asm("msr " TCR2_EL1 ", %[x0]\n\t" >> > + "mrs %[x1], " TCR2_EL1 "\n\t" >> > + : [x1] "=r" (out) >> > + : [x0] "r" (in)); >> > + >> > + if ((out & feature_mask) == in) { >> > + ml_printf("OK\n"); >> > + return 0; >> > + } else { >> > + ml_printf("FAIL: read value %lx != written value %lx\n", >> > + out & feature_mask, in); >> > + return 1; >> > + } >> >> extend this part to check the bits are behaving as the feature dictates >> then we can add a second test like this (Makefile.softmmu-target): >> >> run-asid2-oldcpu: asid2 >> $(call run-test, $<, \ >> $(QEMU) -monitor none -display none \ >> -chardev file$(COMMA)path=$<.out$(COMMA)id=output \ >> $(QEMU_OPTS) $<) >> >> run-asid2-oldcpu: QEMU_OPTS=-M virt -cpu cortex-a72 -display none >> $(QEMU_BASE_ARGS) -kernel >> >> EXTRA_RUNS += run-asid2-oldcpu >> >> Although its a bit clunky - one day I'll get around to converting this >> lot to meson. > > Good idea, but as far as I can see cortex-a72 doesn't implement > FEAT_TCR2, and nor does anything other than cpu-max, so the write and > read to TCR2_EL1 will be undefined behaviour (and causes an error in > the test). I could (and probably should) add a test for FEAT_TCR2 as > well, but it won't test anything more than my original test covers.
Ahh I see - until we have a new CPU type that has FEAT_TCR2 without ASID2 there isn't much point jumping the hoops to test the edge case. I think the most modern non-max CPU we have at the moment is the neoverse-n2. We have TRMs for the -n3 and -v3's now so we could check those to see if we have enough of the features to add them to the list and if they meet the criteria of FEAT_TCR2 without FEAT_ASID2. In the meantime no need to hold this up: Reviewed-by: Alex Bennée <[email protected]> > > Jim -- Alex Bennée Virtualisation Tech Lead @ Linaro
